JPS6340508B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization system for asynchronous digital data for efficient multiplexing when asynchronous digital data is taken into a digital synchronous network in cyclic transmission.

As is well known, cyclic transmission (cyclic data transmission) is a pattern that does not normally occur in combinations of multiple pieces of data and their error control signals (e.g., parity signals). (Unique pattern)
Let be the frame synchronization signal, {frame synchronization signal +
(data + error control signal) x number of data} is defined as one frame, and this is repeated at a constant period to be transmitted many times.

Conventionally, in such cyclic transmission,
The most efficient method for multiplexing asynchronous digital data is the pulse stuff multiplexing method, which is characterized by the fact that the low-speed data to be multiplexed is not processed in any way, and can be processed only between multiplex converters.

In other words, when multiplexing, a clock frequency fine adjustment pulse (stuff pulse) is occasionally inserted into the input pulse train on the low-speed side to apparently synchronize the clock of the input signal and the clock of the multiplexer. This method accurately removes (de-stuff) the previously inserted stuff pulse from the received pulse train and smoothes it back to its original speed. This will be explained in detail below.

The pulse stack multiplex converter is constructed as shown in FIG. input pulse train (this nominal frequency is ₁
shall be. ) is input to the staff circuit 1, and the timing extraction circuit 2 extracts the timing frequency ₁ . This ₁ pulse causes the memory circuit 3 to sequentially store the input pulse train several bits at a time, and the control circuit 5 divides the input pulse train from the clock of the synchronous multiplex circuit 6 to create a clock (this nominal frequency is assumed to be ₂ ). Note that ₂ > ₁ ), the data is read out, transferred to the synchronous multiplexing circuit 6, and multiplexed. At this time, the phase comparison circuit 4 monitors the phase difference between the write clock ₁ and the read clock ₂ , and when this difference exceeds a certain upper limit, the control circuit 5 stops reading and inserts a dummy pulse instead.

On the receiving side, the received pulse train is separated into channels by a synchronous multiplexing/demultiplexing circuit 7 and distributed to a de-staff circuit 8. The received pulse train is sequentially stored in the memory circuit 9 using a write timing signal output from the control circuit 10. Since the write timing signal has phase fluctuations due to destaph, the read timing signal (frequency ₁ ) has the phase fluctuations reduced by the low frequency converter 11 and the voltage controlled oscillator circuit 12.
Then, the contents of the memory circuit 9 are read out and output.

Although the pulse-staff multiplex conversion method has the flexibility of being able to multiplex asynchronous digital signals as is, it is also possible to perform voltage-controlled oscillation by selecting the design of the low-frequency converter 11 and the selection of the insertion position interval of the stuff pulses. Since the phase fluctuation of the output timing signal of the circuit 12 changes greatly, the design is quite complicated, and it is difficult to find a single solution.

The present invention solves the above drawbacks by slightly changing the format of the low-speed side synchronization signal when multiplexing when the pulse train of the low-order group is cyclic and its frame synchronization signal is unique. This aims to shorten the synchronization recovery time of the low-order group pulse train and improve the multiplicity by not performing staff multiplexing.

The present invention provides three types of unique patterns in cyclic data transmission: a unique pattern that can be configured with the minimum number of bits, a unique pattern that can be configured with the minimum number of bits + 1 bit, and a unique pattern that can be configured with the minimum number of bits + 2 bits. This is a frame synchronization method characterized by regarding the seed as a frame synchronization signal.

Next, an embodiment of the present invention will be described based on FIG. 2.

An input pulse train (the nominal clock frequency of which is ₁ ) is input to the input conversion circuit 21, with the frame synchronization signal bit count set to (the minimum number of bits for a unique pattern + 1 bit). Here, ₁ is extracted by the timing extraction circuit 22, and this ₁ pulse causes the memory circuit 23 to sequentially store the input pulse train several bits at a time.
The control circuit 26 divides the frequency of the 7 clock to create a clock (its nominal frequency is ₂ ), and transfers and multiplexes it to the synchronous multiplex circuit 27. At this time, the phase comparison circuit 25 monitors the phase difference between the write clock ₁ and the read clock ₂ , and when this difference exceeds a certain upper limit, the control circuit 26 stops reading and performs the next operation.

If the phase of the read clock is ahead of the phase of the write clock ( ₂ > ₁ ), when the frame synchronization signal is detected by the frame synchronization signal detection circuit 24, the number of bits of the frame synchronization signal is increased by 1 bit, and if it is delayed, Frame synchronization signal detection circuit 24
When a frame synchronization signal is detected, one bit is deleted from the frame synchronization signal. In this way, the frequency of the input pulse train and the clock frequency in the multiplexer are finely adjusted, but since the positions where pulses can be inserted or deleted are limited to the positions where the frame synchronization signal is present, the number of bits in one frame is Assuming n bits, the following relationship must hold between ₁ and ₂ .

₁ (1-1/n) _{2 1} (1+1/n)...(1) For example, if one frame is 1000 bits, ₁
The difference between and ₂ must be within 0.1%.
In the above operation, the pulse train read out from the m input conversion circuits ₂₁ to the synchronous multiplexing circuit 27 by 2 is time-division multiplexed at a speed m times ₂ , and further 2
A synchronization signal different from the frame synchronization signal of 1 is added and sent to the line.

On the receiving side, the synchronization multiplexing and demultiplexing circuit 28 first detects the other synchronization signal, and then separates the pulse train into m pieces by the reverse method of time division multiplexing, and transfers them to the output conversion circuit 29 having a memory circuit, where they are Output to outside. Control circuit 10 and low frequency device 1 in Fig. 1
1 and the voltage controlled oscillation circuit 12 are unnecessary.

With the above operation, the frame synchronization pattern FSP of the output pulse train changes as shown in FIG.
In other words, the input pulse train of the input conversion circuit 21 in FIG. 2 has a period determined by the difference between ₁ and ₂ , and exceeds the determined phase difference. One bit is deleted or one bit is inserted depending on the delay or lead, and then the data is transmitted. On the receiving side, the received pulse train is simply separated into each channel and outputted to the output conversion circuit 29 as a pulse train or '.

According to the present invention, as explained above, by manipulating the frame synchronization signal of the low-order group data, the hardware of the multiplex converter can be simplified, and the multiplicity can be improved by eliminating the need for staff designation pulses. The synchronization pull-in time can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a multiplex converter using the conventional staff multiplexing method, Fig. 2 is a block diagram of a multiplex converter using the method of the present invention, and Fig. 3 is a block diagram of a multiplex converter using the method of the present invention. This is a time chart of a low-order group input pulse train and an output pulse train of the converter. In Figure 1, 1 is a staff circuit, 2 is a timing extraction circuit, 3 is a memory circuit, 4 is a phase comparator circuit, 5 is a control circuit, 6 is a synchronous multiplexing circuit, 7 is a synchronous demultiplexing circuit, and 8 is a destaff circuit. , 9 is a memory circuit, 10 is a control circuit, 11 is a low frequency generator, 12
is a voltage controlled oscillator circuit. In FIG. 2, 21 is an input conversion circuit, 22 is a timing extraction circuit, 23 is a memory circuit, 24 is a frame synchronization signal detection circuit, 25 is a phase comparison circuit, 2
6 is a control circuit, 27 is a synchronous multiplexing circuit, 28 is a synchronous demultiplexing circuit, and 29 is an output conversion circuit.

Claims (1)

[Claims] 1 A plurality of input data pulse trains transmitted by cyclically repeatedly transmitting data having a frame configuration determined by a frame synchronization signal are applied to a synchronous multiplex circuit through a plurality of input conversion circuits, respectively. , each of the input conversion circuits converts the read clock when the phase difference between the memory circuit that sequentially stores the input data pulse train and the write clock and read clock for the memory circuit exceeds a certain upper limit value. If the phase is ahead of the phase of the write clock, the number of bits of the immediately following frame synchronization signal is increased by one bit, and if the phase is delayed, the number of bits of the immediately following frame synchronization signal is deleted by one bit. A cyclic signal is characterized in that three types of unique patterns are considered as frame synchronization signals: a unique pattern that can be configured with a minimum number of bits + 1 bit, and a unique pattern that can be configured with a minimum number of bits + 2 bits. Frame synchronization method in transmission.