JPS6341273B2 - - Google Patents

Description

[Detailed description of the invention]

Industrial Application Field The present invention is applicable to modified Hoffman (hereinafter abbreviated as MH) in facsimile equipment, etc.
The present invention also relates to a large-scale integrated circuit for encoding and decoding image signals that performs encoding and decoding using a modified read (hereinafter abbreviated as MR) encoding method. Conventional configuration and its problems Currently, the image signal encoding method for facsimile is based on the CCITT (International Telegraph and Telephone Consultative Committee).
According to Recommendation T.4, MH
Regarding the encoding method and two-dimensional encoding, the MR encoding method is internationally standardized. Here, the MH encoding method is a method that detects a change point in an encoded line image signal and uses an MH code corresponding to the run length and whether the run is black or white. , a terminating code (hereinafter abbreviated as TC) corresponding to a run length of 0 to 63 as shown in Table 1,
Make-up code for each run length of 64 runs from 64 to 2560 (hereinafter abbreviated as MC)
There is. That is, runs of 64 or more are encoded by an MC followed by a TC.

【table】

[Table] In addition, the above-mentioned MR encoding method detects the change point of the encoded line image signal and the change point of the reference line (line before the encoded line) image signal, and from their relative positions, the encoded line image signal is detected. This is a method that sequentially encodes the In this MR encoding method, the changing points of the encoded line and the reference line are defined as follows. a ₀ : Reference or base point change point on the encoded line At the beginning of the encoded line, a ₀ is placed on the virtual white change point immediately before the first pixel of the line. During encoding of a code line, the position of a ₀ is defined by the previous encoding mode. a ₁ : The first changing point to the right of a ₀ on the encoding line a ₂ : The first changing point to the right of a ₁ on the encoding line b ₁ : Among the changing pixels on the reference line, to the right of a ₀ a ₀
The first change point b ₂ having the opposite color: the first change point to the right of b ₁ on the reference line FIG. 1 shows an example of the positional relationship of the above-mentioned change points.
Further, Table 2 shows the mode classification according to the relative position of the change point and the corresponding code.

[Table] Now, the MH and
Some MR encoding and decoding circuits depend on software from a general-purpose microcomputer (hereinafter abbreviated as MPU), and others rely on dedicated hardware circuits. However, the former has the disadvantage that it is not suitable for high-speed processing because the processing speed is determined by the operating speed of the general-purpose MPU. In the latter case, the encoding circuit counts the distances a ₀ a ₁ , a ₀ b 1 , a _{1 a 2 ,} a ₀ b ₂ between the change points with the change point detection circuit of the reference line and the encoded line. A counter, a circuit that calculates the counted value and outputs the MR encoding mode, a table ROM that converts the mode and counted value into code data corresponding to them, and converts the code data into a continuous data string. Parallel/serial conversion (hereinafter referred to as P/
While it is composed of a circuit (abbreviated as S conversion),
The decoding circuit includes a table ROM circuit that decodes the MR code mode or MH code run length from a serial code data string, and a table ROM circuit that detects change points b ₁ and b ₂ on the reference line and extracts the image signal from the mode. and a circuit that counts the run length and generates an image signal. Further, both the encoding circuit and the decoding circuit require a circuit for setting and controlling each of the constituent circuits. Therefore, although the processing speed can be increased, the disadvantage is that the circuit configuration becomes large-scale and complicated. OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional art. The purpose is to provide integrated LSI. Structure of the Invention The image signal encoding/decoding LSI of the present invention inputs a reference line image signal, an encoded line image signal, and a line enable signal that defines the number of pixels in one line, and detects change points of the image signal and MR. a change point/mode detection circuit that detects the mode of the encoding method;
a decoded line image signal output circuit that outputs a decoded line image signal during decoding; a run length counter circuit that counts the run length of the image signal;
A bit length counter circuit that counts the bit length of the generated code data during encoding is connected to the bus of an external general-purpose microcomputer, and code data can be input and output from this bus. At the same time, a code data input/output circuit equipped with a control register, and a microprogram type sequencer circuit that has primary storage and calculation functions and stores the program and MH code table in the same storage circuit are integrated on a single semiconductor substrate. The change point/mode detection circuit, the decoded line image signal output circuit, the run length counter circuit, the bit length counter circuit, the code data input/output circuit, and The sequencer circuit is connected to a common sequencer bus, and the sequencer circuit executes the program according to an operation mode set in the control register from the external general-purpose microcomputer. It controls other circuits connected to a common sequencer bus and executes encoding and decoding processes for MH and MR encoding methods. processing can be realized at high speed with a common circuit configuration,
Additionally, control and code data management can be done externally.
This can be easily done with an MPU. DESCRIPTION OF EMBODIMENTS FIG. 2 shows an image signal encoding/decoding LSI according to an embodiment of the present invention, in which LSI 1 includes a change point/mode detection circuit 2, a decoded line image signal output circuit 3, and a run length counter. circuit 4, bit length counter circuit 5, code data input/output circuit 6,
and the sequencer circuit 7 are integrally formed on a single semiconductor substrate. Here, the change point/mode detection circuit 2 detects a reference line image signal, an encoded line image signal, and a
A line enable signal that specifies the number of pixels in a line is synchronously input serially, and change points are detected and the MR encoding mode is determined for each pixel from these inputs, and the change point detection information is sent to the sequencer. It is output as a condition signal for the circuit 7, and mode information is output to the sequencer bus. The decoded line image signal output circuit 3 outputs “1” and “1” of the image signal via the sequencer bus during decoding.
It is set to "0". The run length counter circuit 4 counts the run length in synchronization with the input of the image signal, and reads out the counted value and sets the initial value by the sequencer circuit 7 through the sequencer bus. , the carry is used as a condition signal for the sequencer 7. The bit length counter circuit 5 counts the bit length of the code data in synchronization with the serial shift of the code data, and its initial value is set through the sequencer bus, and its carry is held and sent to the sequencer. It is output as a condition signal of the circuit 7. The code data input/output circuit 6 is an external general-purpose
It is connected to the bus of an MPU (not shown), has an interface function with the MPU,
During encoding, serial code data from the sequencer circuit 7 is converted into serial/parallel (hereinafter referred to as S/
(abbreviated as P) and outputs it to the MPU bus. At the time of decoding, the parallel encoded data from the MPU is P/S converted and sent to the sequencer circuit 7.
Output to. In addition, this code data input/output circuit 6
When the sequencer circuit 7 requests the transfer of code data, if the transfer of the external MPU bus is not in time, a stop signal _S14 is sent to the sequencer circuit 7.
Output. Further, the code data input/output circuit 6 has a control register in which the operating mode of the present LSI 1 is set by the external MPU, and the contents of this register can be read out to the sequencer bus. The sequencer circuit 7 is a microprogram type sequencer circuit having temporary storage and calculation functions for information on the sequencer bus, and includes a change point/mode detection circuit 2, a decoded line image signal output circuit 3, a run length signal output circuit 3, and a run length detection circuit 2. The counter circuit 4, bit length counter circuit 5, and code data input/output circuit 6 are connected to the condition signal and the sequencer signal.
Control through the bus. The sequencer circuit 7 also has an MH code data table on its program ROM. FIG. 3 is a block diagram showing details of the change point/mode detection circuit 2 and the decoded line image signal output circuit 3. Among these, the change point/mode detection circuit 2 is
It is structured as follows. 8 is a 5-bit shift register that parallelizes the line enable signal; 9 is an 8-bit shift register that parallelizes the line enable signal and the reference line picture signal ANDed by AND gate 10; 11 is a 5-bit shift register that parallelizes the line enable signal;
This is a 5-bit shift register that parallelizes the encoded line image signal ANDed with the line enable signal by the AND gate 12. These registers 8, 9, and 11 receive input from the sequencer circuit 7 through the sequencer bus. The shift operation is performed in synchronization with the image signal request signal _S1 . 13 selects the output of the fifth bit (input side is the first bit) of the shift register 11 during encoding, and the decoded line image signal output from the decoded line image signal output circuit 3 during decoding. This is a selector that outputs the run color signal _S2 . 14 is an exclusive OR gate (hereinafter abbreviated as EOR) which takes the run color signal _S2 as one input and takes the output of the fourth bit of the shift register 11 as the other input. 15 is 8
This is an EOR group consisting of EORs, and the eight EORs have the run color signal _S2 as one input in common, and shift and
The output of each bit of register 9 is used as the input of the other. 16 is a flip-flop for b ₁ detection flag (hereinafter abbreviated as b ₁ FF), which is used when a programmable logic array (hereinafter abbreviated as PLA) 17, which will be described later, detects b ₁ from a ₁ . ,same
Set to "1" by PLA17. 18 is a flip-flop for horizontal mode detection flag (hereinafter abbreviated as horizontal mode FF);
While PLA 7 is detecting the horizontal mode, the same PLA17
It is set to "1" by Reference numeral 19 denotes a control register, which determines the operating mode of this change point/mode detection circuit 2, that is, MH method and
The distinction between MR method and encoding and decoding is set from the sequencer circuit 7 through the sequencer bus. The PLA17 has shift register 8, EOR1
4, EOR group 15, b ₁ FF16, horizontal mode FF18
With the output of register 19 as input, signals S ₃ to _{S 8} are output as described below using a preprogrammed product term (hereinafter abbreviated as PT). In other words, when PLA17 encodes MH,
When the output of EOR14 is "1", it is assumed that a change point on the encoded line has been detected, and the signal _S3 is set to "1".
shall be. Also, during MR encoding, when the output pattern of each bit of EOR 14, EOR group 15, and shift register 8 corresponds to one of the three modes of MR encoding, a signal is detected as mode detection.
_S3 is set to "1", and mode information indicating the type of detected mode is encoded using signals _S4 to _S7 and output. Note that this mode information can be output to the sequencer bus through the buffer 20. In addition, the PLA 17 performs MR decoding at the time of MR decoding.
The outputs of the 5th and 4th bits, the 4th and 3rd bits, the 3rd and 2nd bits, and the 2nd and 1st bits of the EOR group 15 are all "0".
and becomes "1", the signals S ₄ to _{S 7} are respectively set to "1" (the output of the EOR whose input is the output of the 1st bit to the 5th bit of the shift register 9 is
(These are the outputs of the first to fifth bits of the EOR group 15, respectively). Furthermore, the PLA 17 sets S3 to " ₁ " when the outputs of the fifth bit and the fourth bit are "1" and "0".
shall be. Furthermore, during MH/MR encoding and decoding, when the fourth bit and fifth bit of the shift register 8 are "0" and "1", respectively, the PLA 17 outputs the signal S as the end of one line. Let ₈ be “1”. Note that the signals S ₂ to _{S 8} serve as condition signals for the sequencer circuit 7. Reference numeral 21 denotes an address decoder that selects input and output of information on the sequencer bus, and uses signals S ₁₇ and S ₁₈ output from an instruction decoder 56 of the sequencer circuit 7, which will be described later, as enable signals. Here, signal _S17 is an enable signal for outputting information to the sequencer bus, and signal _S18 is an enable signal for inputting information on the sequencer bus. On the other hand, the decoded line image signal output circuit 3 is composed of a flip-flop (hereinafter abbreviated as FF) 22 connected to a sequence bus and an address decoder 23. Here, the FF
22 sets the decoded line image signal to “0” or “1”
The address decoder 23
is for selecting FF22. Further, the address decoder 23 uses the signal _S18 as an enable signal. FIG. 4 is a block diagram showing details of the run length counter circuit 4, bit length counter circuit 5, and code data input/output circuit 6. Of these, the run length counter circuit 4 is configured as follows. 24 is a 6-bit counter that counts in synchronization with the image signal request signal _S1 ;
A 6-bit counter 25 counts the carries of the counter 24, and the carry signal _S9 of this counter 25 becomes a condition signal for the sequencer circuit 7.
Further, the initial values of the counters 24 and 25 are set by the sequencer circuit 7 through the sequencer bus, and the count values are set by the sequencer circuit 7 through the sequencer bus.
output to the sequencer bus through An address decoder 28 sets the counters 24 and 25 and outputs enable signals to the buffers 26 and 27. This address decoder 28 uses the signals S ₁₇ and S ₁₈ as enable signals. The bit length counter circuit 5 is constructed as follows. 29 is an 11-bit counter that performs counting in synchronization with the code data shift signal _S10 , and its upper 8 bits are sent to the sequencer circuit 7.
Configured through the bus. Also, this counter 2
9's carry is held by FF30, and the same FF3
The output signal S ₁₁ of 0 becomes a condition signal for the sequencer 7. 31 is an address decoder for setting the counter 29; And FF30 is this address
The output of the decoder 31 resets the counter 29 when it is set. Note that the address decoder 31 uses the signal _S18 as an enable signal. The code data input/output circuit 6 is configured as follows. 32 is a shift register which performs S/P conversion of code data during encoding and P/S conversion during decoding. That is, during encoding, serial code data from the sequencer circuit 7 is shifted to the shift signal S10 in synchronization with the code data shift signal _S10 .
The code data shift signal S10 is serially input to the register 32, and the 3-bit counter 33 converts the code data shift signal _S10 into 8
At each count, 8 bits are transferred in parallel from the shift register 32 to the register 34. Furthermore, during decoding, the code data written on the register 35 from the external MPU bus is transferred to the shift register 32 in 8-bit parallel fashion, and this transferred data is further converted into a code data shift signal _S10 . Synchronously, the code data S ₁₃ is serially output to the sequencer circuit 7 (note that the transfer of code data from the register 35 to the shift register 32 also involves the counter 33 counting the code data shift signal S ₁₀ by 8). (performed every time) 36 is a bus interface circuit that controls the transfer of the encoded data mentioned above and controls the external MPU.
Interfacing control signals with the bus. In addition, this bus interface circuit 36 is configured so that when the counter 33 counts 8 during encoding, if the contents of the register 34 have not been read out to the external MPU, and during decoding, the counter 33 counts 8. When register 35
If code data is not written in the respective sequencer circuits, the stop signal _S14 to the sequencer circuit 7 is set to "1". Reference numeral 37 denotes a control register group in which the operating mode and other control information of the LSI 1 are set by the external MPU, and the contents of this control register group 37 are outputted to the sequencer bus through a buffer 38. 39 shows the internal status of this LSI1 externally.
This is a status register that notifies the MPU.
The contents of this status register 39 are set through the sequencer bus. 40 is batshua 3
8 and to set the status register 39.
It's a recorder. Note that this address decoder 40 uses the signals S ₁₇ and S ₁₈ as enable signals. FIG. 5 is a block diagram showing details of the sequencer circuit 7. 41 is a ROM that stores both microinstructions for encoding and decoding control and an MH code table, and has a capacity of 20 bits per word and a maximum of 2048 words. Note that this LSI1 uses the same
The program and code table are stored on the ROM 41, and the function of the decoding table ROM is replaced by the program, so the ROM is combined into one and the configuration is reduced. The microinstruction is input to a pipeline register (hereinafter abbreviated as PLR) 42 and executed. On the other hand, the code data of the MH code table is input to a 20-bit register 43, passed through buffers 44, 45, and 46, and output to the sequencer bus. FIG. 6 shows the format of the code table. The addresses of the ROM 41 include the following four types of addresses: a direct address A ₁ by a microinstruction on the PLR 42, a fixed address A ₂ for program breaks, an address with an offset by the adder 47 A ₃ , and a program counter register. There is a PCR address _A4 (hereinafter abbreviated as PCR) 48. These four types of addresses A ₁ , A ₂ , A ₃ , and A ₄ are selected by the selector 49. 50 is an incrementer that adds 1 to the address output from the selector 49; 51 is a stack register that stores the subroutine return address; and 52 is the return address and the direct address _A1.
A selector 53 inputs an offset based on the microinstruction on the PLR 42 and an offset based on the information on the sequencer bus, and selects one of them as the reference address for the address with offset _A3 . This is a selector for selecting one as the offset value of the address with offset _A3 . In addition, the above address with offset
A ₃ is obtained by adding the addresses output from selectors 52 and 53 using adder 47. 54 is a selector for selecting a condition signal to be determined using a branch microinstruction as a select signal; 55;
is an EOL detector that detects a line synchronization code (hereinafter abbreviated as EOL) pattern "000000000001", and has a 12-bit shift register and a decoder that receives the signal _S13 as input.
Shifting is performed in synchronization with the shift signal _S10 , and when EOL is detected, the EOL detection signal _S15 is set to "1".
The EOL detector 15 also outputs the output of the shift register as a signal _S16 . Reference numeral 56 denotes an instruction decoder, which receives the microinstruction instruction field (variable length of 4 to 9 bits) from the PLR 42, the output of the selector 54, and the signals S ₁₄ and S _{15 .}
and _S16 , and outputs the control signal _S50 inside the sequencer circuit 7 and the control signals _S1 , _S10 , _S17 , and _S18 of the sequencer bus. Also,
This instruction decoder 56 has a stop signal _S14 of "1".
When this happens, all control signals are turned off and instruction execution is stopped. In addition, the EOL detection signal
When _S15 becomes "1", the selector 49 selects the fixed address _A2 as the address for the next execution instruction.
is selected. A buffer 57 outputs data directly from the microinstructions on the PLR 42 to the sequencer bus. 58 is a computing unit (hereinafter abbreviated as ALU)
and the sequencer bus information and 8 bits
The calculations shown in Table 3 are performed using the output of a readable and writable memory (hereinafter abbreviated as RAM) 59 having the configuration shown in FIG. The operation result of this ALU 58 is inputted again to the RAM 59, and the status of the operation result (carry, all "0", all "1", sign bit) is inputted to the register 60. The output of the register 60 becomes the input of the selector 54, thereby becoming a condition signal for the sequencer 7, and the carry bit is the code data _S12.
becomes. The contents of RAM 59 are output to the sequencer bus through ALU 58 and buffer 61. 62 is an address decoder that outputs enable signals to buffers 44, 45, and 46.
This address decoder 62 uses the signals S ₁₇ and S ₁₈ as enable signals.

[Table] Next, the encoding and decoding operations of this LSI 1 will be explained. This LSI 1 is activated by setting an operation mode on the control register group 37 in the code data input/output circuit 6 from the external MPU. and,
According to the microinstructions programmed on the ROM 41, the contents of the control register 37 are judged by the ALU 58 through the sequencer bus, and according to the judgment result, the following steps are performed: MH encoding, MH decoding, MR encoding, MR decoding. The program branches to each program, and the processing is executed as follows. (1) MH encoding process First, the counters 24 and 25 of the run length counter circuit 4 are set to “0”, and the PLA
By outputting the picture signal request signal _S1 from the instruction decoder 56, the encoded line picture signal and the line enable signal are sent to the change point/mode detection circuit 2 until the output signal S3 of 17 becomes " ₁ ". is input. At this time, counters 24, 2
5, there are run length values corresponding to TC and MC, respectively. Next, the value of the counter 25 is determined and is “0”.
Otherwise, the run color is determined by the run color signal _S2 input from the fifth bit of the shift register 11 to the instruction decoder 56 through the selectors 13 and 54, and the MC of "white" or "black" on the ROM 41 is determined. The MC corresponding to the value of the counter 25 from the table is set in the register 43 by the offset address _A3 . The code data set on the register 43 has a code length of 4 bits and a code of maximum 16 bits, and is transferred to 3 bytes on the RAM 59 through the sequencer bus, shifted by the code length by the ALU 58, and sent to the signal _S12. is output as
At this time, the code data shift signal _S10 is turned on for every 1-bit shift, and the signal _S12 is input to the shift register 32. Further, when the counter 25 is "0" and when the counter 25 is not "0", the data is input to the shift register 32 as described above.
After the output of the MC is completed, the TC corresponding to the value of the counter 24 is output to the shift register 32 in the same manner as in the case of the MC. The code data on the shift register 32 is transferred every 8 bits to a register 34, and further read out from this register 34 to the external MPU bus. Next, if the output signal _S8 of the PLA 17 is not "1", the counters 24 and 25 are set to "0" again, and the same process as described above is repeated. Furthermore, at the start of processing for one line, the minimum bit length of code data for one line is set in the counter 29, and if the signal _S8 is 1, the carry hold signal _S11 of the counter 29 is determined, and the same signal Fill bits ("0") are input to shift register 32 until _S11 becomes "1". Thereafter, encoding is performed line by line in the same manner (in order to avoid complicating the explanation, a description of processing such as initial setting for each line is omitted). (2) MH decoding process First, encoded data is sequentially written from the external MPU bus to the register 35, and then transferred from the same register 35 to the shift register 32.
Thereafter, the shift register 32 is shifted by the code data shift signal _S10 until the EOL detection signal _S15 becomes "1".
is output serially as signal _S13 .
When the EOL detection signal _S15 becomes "1", the program branches to the beginning of the decoding process for each line according to the fixed address _A2 , and the EOL detector 55
Regarding the serial code data _S16 outputted from the EOL code, "1" and "0" are sequentially determined for each bit starting from the next bit of the EOL code, and the run length value corresponding to the code is decoded. The microinstructions used at this time are three instructions 11, 12, and 13 shown in FIG. 7, and FIG. 8 shows an example of the program. However, in FIG. 8, the * mark indicates an address with an offset (moves to the encoded line image signal output program of the TC). Further, run length values corresponding to the MH code are set in counters 24 and 25 by instructions 12 and 13. Next, the image signal request signal _S1 is turned on until the carry signal S9 of the counter 25 becomes " ₁ ", and the FF 22 outputs the decoded line image signal. Here, FF22 is set to “0” (white) through the sequencer bus when detecting the EOL code,
After that, after outputting the decoded line image signal of TC,
“0” and “1” are inverted. From then on, until the EOL detection signal _S15 becomes “1”,
In the same manner as described above, the decoding of the MH code and the output of the decoded line image signal are repeated, and one line decoding processing is performed. (3) MR encoding process First, the counters 24 and ₂₅ are set to " ₀ ", and the encoded line picture signal, reference A line image signal and a line enable signal are input to a change point/mode detection circuit 2. When the signal _S3 becomes "1", the mode information of the MR code encoded on the signals _S4 to _S7 is output, and this mode information is output to the sequencer bus through the buffer 20, and this Address with offset that offsets the contents of the bus
A ₃ branches to the processing program for each mode. In the processing program for each mode, the code and code length corresponding to each mode are set on the RAM 59, and the code data is transferred to the shift register 32 in the same manner as in the MH encoding process. And in case of horizontal mode, further
Similarly to the MH encoding process, the MH code is transferred from the values of the counters 24 and 25 to the shift register 32, and the counters 24 and 25 are set to "0" again, and the next encoded line image signal is transferred. Runs are also subjected to MH encoding processing. Next, if the output signal _S8 of the PLA 17 is not "1", the counters 24 and 25 are set to "0" again, and the same process is repeated. The processing after the signal _S8 becomes "1" is the same as the MH encoding processing described above. (4) MR decoding process Similar to the MH decoding process described above, external
When an EOL code is detected from the code data from the MPU bus, decoding of one line is started. The serial code data _S16 outputted from the EOL detector 55 is sequentially determined to be "1" or "0" bit by bit according to the instruction _I1 , and the program branches according to the mode corresponding to the code. In pass mode, change point b ₁ is detected and
The output signal S ₄ of the PLA 17 becomes "1", and then the change point b ₂ is detected, and the image signal request signal continues until the output signal S ₃ of the PLA 17 becomes "1".
_S1 is turned on, and the FF 22 outputs a decoded line image signal. In horizontal mode, the following code data S ₁₆
is used as the MH code, two runs of MH decoding processing are performed, and the FF 22 outputs a decoded line image signal. In vertical mode, V(0), V _L (1), V _L (2), V _L
In the case of (3), the output signals S ₄ , S ₅ , S ₆ ,
The signal S ₁ is turned on until S ₇ becomes “1”,
After the decoded line image signal is output from the FF 22, the FF 22 is inverted. In addition, in the case of V _R (1), V _R (2), and V _R (3), PLA1
After the image signal request signal S ₁ is turned on until the output signal S ₄ of 7 becomes “1”,
The image signal request signal _S1 is turned on twice, twice, and three times, and the decoded line image signal is output, and then the FF 22 is inverted. FIG. 9 is a flowchart showing an outline of the processing for each mode described above. Thereafter, the EOL detection signal _S15 becomes “1” in the same way.
The decoding of each mode and the output of the decoded line image signal are repeated until the decoding process for one line is performed. Note that in the case of MR decoding processing, the decoding processing starts after the reference line picture signal and line enable signal are each input to shift registers 8 and 9 in 5 bits, so the decoded line picture signal is 5 bits long. Output is delayed. 10th
If the MR encoding process is shown in Figure a, then Figure 10 is shown in b.
A timing diagram of an encoded line picture signal, a reference line picture signal, and a line enable signal in the case of MR decoding processing is shown. Effects of the Invention As described above, the image signal encoding/decoding of the present invention
(a) Since the LSI has an interface function with an external MPU bus, control and code data management can be easily performed using an external MPU. (b) Data processing is performed by a micro-programmed sequencer circuit and hardware circuit, and there is no need for an external MPU to directly process data, so processing speed can be increased. (c) Encoding and decoding processing using the MH/MR method can be realized with a common circuit configuration, and the program and code table are stored in the same memory circuit in the sequencer circuit, and each component circuit is made of a single semiconductor. Since it is integrally formed on the substrate, the circuit can be made smaller and its reliability can be improved. You can obtain excellent effects such as

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of changes in the MR encoding system, FIG. 2 is a block diagram of an image signal encoding/decoding LSI according to an embodiment of the present invention, and FIG. 3 is a diagram of the LSI described above.
FIG. 4 is a block diagram of the change point/mode detection circuit and the decoded line image signal output circuit in
A block diagram of a run length counter circuit, a bit length counter circuit, and a code data input/output circuit in an LSI, FIG. 5 is a block diagram of a sequencer circuit in the LSI, and FIG.
FIG. 7 is a diagram showing the configuration and format of the code table in the ROM 41 in the sequencer circuit shown in FIG.
9 is a flowchart showing a part of the program for decoding the MH code stored in the ROM 41. FIG. 9 is a flowchart showing a decoding program for each mode of the MR code. In FIG. 10, a and b are the LSIs respectively. FIG. 3 is a timing diagram of a line enable signal, a reference line picture signal, an encoded line picture signal, a decoded line picture signal, and a picture signal request signal _S1 in FIG. 1... Image signal encoding/decoding LSI, 2... Change point/mode detection circuit, 3... Decoded line image signal output circuit, 4... Run length counter circuit, 5... Bit length counter circuit. Counter circuit, 6
... code data input/output circuit, 7 ... sequencer circuit, 41 ... ROM.

Claims (1)

[Claims] 1. A change point/mode detection circuit that detects a change point of an image signal and a mode of a modified read encoding method, and a composite line image signal output circuit that outputs a decoded line image signal during decoding. , a run length counter circuit that counts the run length of the image signal, a bit length counter circuit that counts the bit length of the code data generated during encoding, and an external general-purpose microcomputer circuit. It has a coded data input/output circuit that is connected to the bus and is capable of inputting and outputting coded data to and from the bus, and has primary storage and calculation functions, and stores a program and a modified Hoffman code table in the same storage circuit. An image signal encoding/decoding system characterized in that a micro-programmed sequencer circuit is integrally formed on a single semiconductor substrate, and each of the circuits is connected to a common sequencer bus. Scale integrated circuit. 2. By providing a control register in the code data input/output circuit, and executing the program of the sequencer circuit from a general-purpose microcomputer according to the operation mode set in the control register,
The image signal code according to claim 1, which controls other circuits connected to a common sequencer bus to execute encoding and decoding processes of Modified Hoffman and Modified Read encoding systems. Large-scale integrated circuit for encoding and decoding.