JPS6342413B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly a transistor having high frequency characteristics.

Conventionally, transistors are used by connecting several or tens of divided cells with wire bonds, but in this case, the balance tends to be lost due to variations in the characteristics of each cell, and the output, This will reduce load fluctuation tolerance and efficiency. To prevent this, a method is used in which all cells are connected with electrodes to eliminate imbalance. However, if a method of connecting all cells with electrodes is used, the additional capacitance due to the routing of the electrodes will increase and the high frequency characteristics will deteriorate. Therefore, a method has been used to ensure electromigration of the electrode by making the width of the electrode in the routed portion as thin as possible and increasing the height of the electrode. In order to increase the height of the electrode, a method is used in which the electrode is formed in two steps. The conventional method will be further explained below with reference to the drawings.

FIG. 1 is a plan view showing cells on a wafer before electrode formation. Cells 2 are regularly arranged on a wafer 1. FIG. 2 shows an example of an enlarged view of one cell 2 in FIG.
It consists of a base region 4 and a high concentration base region 5. FIG. 3 is a diagram showing the state after electrode formation, and is an enlarged view of part A in FIG. 1 after electrode formation.
Cell 2 is connected by. Figure 4 shows cell 2
FIG. 3 is an enlarged view after electrode formation. In Figure 4,
The same reference numerals as in FIG. 2 indicate the same parts, indicating that the emitter region 3 and the high concentration base region 5 are connected by an electrode 6. In this way, in the example shown in FIG. 3, six cells 2 are connected by electrodes 6 to operate as a transistor.

FIG. 5 is a diagram showing the manufacturing process of electrode formation in the conventional cell shown in FIGS. 3 and 4, and FIG. 5a is a diagram before electrode formation, and is an enlarged cross-sectional view of FIG. 1. . A cell 2 and an oxide film 7 are formed on a wafer 1. FIG. 5b is a cross-sectional view after the first electrode formation, showing the electrode 8a and the part 9 where the electrode 8a does not exist.
There is. The portion 9 where the electrode 8a is not present corresponds to the portion where the electrode 6 is cut in FIG. Figure 5c
is a cross-sectional view after the second electrode formation, and there is an additionally formed electrode 8b, which forms a thick electrode together with the electrode 8a.

FIG. 6 is a diagram illustrating in more detail the manufacturing process for forming the electrode in FIG. 5, where the same reference numerals as in FIG. In the sixth example, sputtered gold 10 used for electrolytic plating during electrode formation was sputtered, resist was coated on top of the sputtered gold, mask alignment was performed, and resist 11 was left in the areas where electrodes were not to be formed.
Figure b. FIG. 6c is a diagram in which electrode plating has been performed on it to form a first electrode 8a.
FIG. 6d is a diagram showing the inside of the cell 2 coated with resist 12 in order to form the second additionally formed electrode 8b, and then electrolytically plated to form the additionally formed electrode 8b. FIG. 6e is a diagram in which all the resists 11 and 12 have been removed and electrode formation has been completed.

Conventionally, electrodes have been formed as described above, but since the electrode formation is done in two steps, two sets of masks are required for electrode formation, and two sets are required for each number of cells. However, the disadvantage was that it required a large number of masks, making it uneconomical.

In order to solve the above-mentioned drawbacks, this invention reduces the number of required masks by half by creating one type of mask for forming electrodes inside the cell and creating masks for forming bonding pads and routing electrodes outside the cell for each number of cells. This has improved economic efficiency. Hereinafter, this invention will be explained in detail using the drawings.

FIG. 7 is a cross-sectional view of a wafer at each step showing a manufacturing method according to an embodiment of the present invention, and the same reference numerals as in FIG. 6 indicate the same parts. FIG. 7a is a diagram before electrode formation, and FIG. 7b is a diagram before electrolytic plating, in which sputtered gold 10 used for electrolytic plating during electrode formation is sputtered, resist 11 is coated on top of the sputtered gold 10, and mask alignment is performed. By doing this, the resist is removed only from the bonding pads inside and outside the cell 2 and from the electrode portions connected to the lead-out electrodes, leaving the resist 11. FIG. 7c shows the first electrolytic plating process to form an electrode 8a. Furthermore, as shown in Figure 7d,
The resist 12 is coated with a resist, and mask alignment is performed using a mask for forming a bonding pad and a routing electrode to form an electrode at a connection portion with the bonding pad and routing electrode, that is, an electrode 8b outside the cell 2. leave the
Apply electrolytic plating. FIG. 7e is a diagram after all the resist has been removed and electrode formation has been completed.

In the manufacturing method of the present invention described above, the electrodes outside the cell are formed using the bonding pad and the mask for forming the leading electrode.
There is an advantage that the number of required masks can be halved without increasing the number of steps.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the arrangement of cells on a wafer before electrode formation, FIG. 2 is an enlarged plan view of one cell in FIG. 1, and FIG. 3 is a plan view after electrode formation.
Fig. 4 is an enlarged plan view of the inside of the cell in Fig. 3, Fig. 5 is a sectional view of the wafer at each step of conventional electrode formation, and Fig. 6 is a detailed view of the manufacturing method of conventional electrode formation at each step. FIG. 7 is a sectional view of a wafer at each step showing an embodiment of the present invention. In the figure, 1 is a wafer, 2 is a cell, 3 is an emitter region, 4 is a base region, 5 is a high concentration base region, 6
7 is an electrode, 7 is an oxide film, 8a is an electrode, 8b is an additionally formed electrode, 9 is a portion where no electrode is formed, 10 is sputtered gold, and 11 and 12 are resists.

Claims (1)

[Claims] 1. In electrode formation of a semiconductor device in which multiple cells are connected by routed electrodes, the electrodes inside the cells are formed using a mask, and then the bonding pads and the routed electrodes outside the cells are formed by bonding. 1. A method for manufacturing a semiconductor device, characterized in that the manufacturing method is carried out using a mask for forming pads and routed electrodes.