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JPS6342862B2 - - Google Patents
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JPS6342862B2 - - Google Patents

Info

Publication number
JPS6342862B2
JPS6342862B2 JP56059749A JP5974981A JPS6342862B2 JP S6342862 B2 JPS6342862 B2 JP S6342862B2 JP 56059749 A JP56059749 A JP 56059749A JP 5974981 A JP5974981 A JP 5974981A JP S6342862 B2 JPS6342862 B2 JP S6342862B2
Authority
JP
Japan
Prior art keywords
silicon
thin film
film
silicon thin
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56059749A
Other languages
Japanese (ja)
Other versions
JPS57176741A (en
Inventor
Hiroshi Tetsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP56059749A priority Critical patent/JPS57176741A/en
Publication of JPS57176741A publication Critical patent/JPS57176741A/en
Publication of JPS6342862B2 publication Critical patent/JPS6342862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 この発明は、半導体装置の製造方法の改良に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a semiconductor device.

従来の半導体装置の製造方法のうち、SOS−
MOS構造のもののゲート電極形成工程までの断
面図を第1図a〜d,e〜hに示す。第1図a〜
dは活性領域の分離に空間分離を用いた工程図、
第1図e〜hはコプレーナ技術を用いた工程図で
ある。
Among the conventional manufacturing methods for semiconductor devices, SOS-
Cross-sectional views of the MOS structure up to the step of forming the gate electrode are shown in FIGS. 1a to 1d and e to h. Figure 1 a~
d is a process diagram using spatial separation to separate active regions;
Figures 1e to 1h are process diagrams using the coplanar technology.

まず、第1図a〜dの工程を説明する。第1図
aに示すように、サフアイヤ基板101上のシリ
コン単結晶層102の上にシリコン酸化膜すなわ
ちSiO2膜103を形成する。次に、第1図bに
示すようにSiO2膜103の活性領域外の部分を
パターニングし、SiO2膜103をマスクとして
シリコン単結晶層102を選択エツチングする。
この後、第1図cに示すようにSiO2膜103を
除去しゲート酸化膜104を形成する。なおここ
で、イオン注入工程などは省略する。次に第1図
dに示すようにゲート電極105を形成する。
First, the steps shown in FIGS. 1A to 1D will be explained. As shown in FIG. 1a, a silicon oxide film, that is, a SiO 2 film 103, is formed on a silicon single crystal layer 102 on a sapphire substrate 101. As shown in FIG. Next, as shown in FIG. 1B, a portion of the SiO 2 film 103 outside the active region is patterned, and the silicon single crystal layer 102 is selectively etched using the SiO 2 film 103 as a mask.
Thereafter, as shown in FIG. 1c, the SiO 2 film 103 is removed and a gate oxide film 104 is formed. Note that the ion implantation process and the like are omitted here. Next, a gate electrode 105 is formed as shown in FIG. 1d.

この第1図a〜dの製造方法で得たものは、第
1図cの工程で形成したゲート酸化膜104の端
部106(第1図d参照)の厚さが十分でなく、
ゲート電極105とシリコン単結晶層102との
間の絶縁破壊強度が減少し、信頼性に欠けるとい
う欠点があつた。
In the case obtained by the manufacturing method shown in FIGS. 1a to 1d, the end portion 106 (see FIG. 1d) of the gate oxide film 104 formed in the step shown in FIG. 1c is not sufficiently thick.
There was a drawback that the dielectric breakdown strength between the gate electrode 105 and the silicon single crystal layer 102 was reduced, resulting in a lack of reliability.

第1図e〜hは、前記欠点を除去するために考
えられた工程であり、第1図eに示すように、サ
フアイヤ基板101上のシリコン単結晶層102
上に、SiO2膜107、Si3N4膜108、SiO2膜1
09を順次形成する。次に第1図fに示すように
SiO2膜109の活性領域外をパターニングし、
これをマスクとして、Si3N4膜108、SiO2膜1
07を選択エツチングし、さらにシリコン単結晶
層102を約半分の厚さにエツチングする。次
に、第1図gに示すように、これを選択酸化して
酸化膜110を形成し、SiO2膜109を除去す
る。さらに、第1図hに示すようにSi3N4膜10
8、SiO2膜107を除去した後、酸化膜110
と一体にゲート酸化膜111を形成し、ゲート電
極112を形成する。
1e to 1h show the steps considered to eliminate the above-mentioned defects. As shown in FIG. 1e, the silicon single crystal layer 102 on the sapphire substrate 101 is
Above, SiO 2 film 107, Si 3 N 4 film 108, SiO 2 film 1
09 are formed one after another. Next, as shown in Figure 1 f
Patterning the outside of the active region of the SiO 2 film 109,
Using this as a mask, Si 3 N 4 film 108, SiO 2 film 1
07 is selectively etched, and the silicon single crystal layer 102 is further etched to approximately half the thickness. Next, as shown in FIG. 1g, this is selectively oxidized to form an oxide film 110, and the SiO 2 film 109 is removed. Furthermore, as shown in FIG. 1h, a Si 3 N 4 film 10
8. After removing the SiO 2 film 107, the oxide film 110
A gate oxide film 111 is formed integrally with the gate electrode 112.

この第1図e〜hの製造方法によつて得たもの
は、前述した第1図dに示されるような活性領域
すなわちゲート酸化膜104の端部106の絶縁
破壊強度の減少を抑えられる。しかし、選択酸化
を行ない非活性領域を酸化してしまうには、活性
領域間に大きな距離を必要とし、高密度化の妨げ
となる欠点があつた。
The product obtained by the manufacturing method shown in FIGS. 1e to 1h can suppress the reduction in dielectric breakdown strength of the active region, that is, the end portion 106 of the gate oxide film 104, as shown in FIG. 1d. However, performing selective oxidation to oxidize non-active regions requires a large distance between active regions, which has the drawback of hindering high density.

この発明は、前述した欠点を除去しようとする
ものであつて、シリコン単結晶層のマスク層で覆
われない部分をエツチングしてサフアイヤを露出
させた後、ウエーハの主表面全面にシリコン薄膜
を形成し、このシリコン薄膜を酸化処理して酸化
膜に変換することにより、素子の信頼性を高め、
高密度化を達成できる半導体装置の製造方法を提
供することを目的としている。
This invention is an attempt to eliminate the above-mentioned drawbacks, and after etching the portion of the silicon single crystal layer that is not covered by the mask layer to expose the sapphire, a silicon thin film is formed over the entire main surface of the wafer. By oxidizing this silicon thin film and converting it into an oxide film, we can improve the reliability of the device and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can achieve high density.

以下、この発明による半導体装置の製造方法に
つき詳細に説明する。
Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained in detail.

第2図a〜dは、この発明の一実施例による
SOS構造のもののゲート電極形成工程までの断面
図である。第2図a〜dにおいて、201はサフ
アイヤ基板、202はシリコン単結晶層、203
はシリコン酸化膜すなわちSiO2膜、204は多
結晶または非結晶のシリコン薄膜、205はシリ
コン薄膜を酸化処理した酸化膜である。
FIGS. 2a to 2d are according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the SOS structure up to the step of forming a gate electrode. In FIGS. 2a to 2d, 201 is a sapphire substrate, 202 is a silicon single crystal layer, and 203 is a sapphire substrate.
204 is a polycrystalline or amorphous silicon thin film, and 205 is an oxide film obtained by oxidizing the silicon thin film.

まず、第2図aに示すようにサフアイヤ基板2
01上のシリコン単結晶層202上にSiO2膜2
03を形成する。次に第2図bに示すように、
SiO2膜203の活性領域外をパターニングし、
これを耐シリコンエツチング材料となるマスク層
として、シリコン単結晶層202を選択エツチン
グし、サフアイヤ基板201を露出させる。この
後、第2図cに示すように、SiO2膜203を除
去し、露出させたサフアイヤ基板201上を含む
ウエーハの主表面全面にシリコン薄膜204を形
成する。この場合に、シリコン薄膜204の厚さ
は次に行なうゲート酸化処理で形成するゲート酸
化膜の厚さのほぼ1/2以下の厚さとする。また、
シリコン薄膜204は多結晶シリコンまたは非晶
質シリコンとする。次に、第2図dに示すよう
に、酸化処理によつて、シリコン単結晶層202
上にゲート酸化膜205を形成すると同時に、前
記シリコン薄膜204を酸化膜205に変換す
る。なお、図示してないが、ゲート酸化膜205
上にゲート電極を形成することは、前述した従来
の方法と同様である。
First, as shown in FIG. 2a, the sapphire substrate 2
SiO 2 film 2 on silicon single crystal layer 202 on 01
Form 03. Next, as shown in Figure 2b,
Patterning the outside of the active region of the SiO 2 film 203,
Using this as a mask layer serving as a silicon etching-resistant material, the silicon single crystal layer 202 is selectively etched to expose the sapphire substrate 201. Thereafter, as shown in FIG. 2c, the SiO 2 film 203 is removed and a silicon thin film 204 is formed over the entire main surface of the wafer including the exposed sapphire substrate 201. In this case, the thickness of the silicon thin film 204 is set to approximately 1/2 or less of the thickness of the gate oxide film to be formed in the next gate oxidation process. Also,
The silicon thin film 204 is made of polycrystalline silicon or amorphous silicon. Next, as shown in FIG. 2d, the silicon single crystal layer 202 is
At the same time as forming a gate oxide film 205 thereon, the silicon thin film 204 is converted into an oxide film 205. Although not shown, the gate oxide film 205
Forming a gate electrode thereon is similar to the conventional method described above.

以上説明したように、この発明の一実施例によ
る製造方法では、非活性領域のシリコン単結晶層
をすべて除去した後、ウエーハの主表面全面にシ
リコン薄膜を形成し、これを酸化してしまうた
め、十分に活性領域を分離させることができ、ゲ
ート絶縁破壊強度の減少という従来の製造方法に
よつて生ずる欠点を克服することができる。ま
た、ゲート酸化処理ですべて酸化してしまう程度
の厚さのシリコン薄膜を形成するので、コプレー
ナ構造に必要な厚いシリコンの選択酸化を行なう
必要がないことにより、素子を高密度に集積する
ことが可能となる。さらに、前記シリコン薄膜を
予定ゲート酸化膜厚のほぼ1/2の厚さにしておく
と、この酸化膜への変換工程と同時にゲート酸化
膜の形成ができる。したがつて、SOS構造の素子
の信頼性を高め、高密度化を達成することができ
る。
As explained above, in the manufacturing method according to one embodiment of the present invention, after all the silicon single crystal layer in the inactive region is removed, a silicon thin film is formed on the entire main surface of the wafer, and this is oxidized. , the active region can be sufficiently isolated to overcome the disadvantage caused by conventional fabrication methods of reduced gate breakdown strength. In addition, since a thin silicon film is formed that is so thick that it is completely oxidized during gate oxidation, there is no need to selectively oxidize thick silicon, which is required for coplanar structures, making it possible to integrate elements at a high density. It becomes possible. Furthermore, if the silicon thin film is made to have a thickness approximately half of the planned gate oxide film thickness, the gate oxide film can be formed at the same time as the conversion process to this oxide film. Therefore, the reliability of the SOS structure element can be improved and higher density can be achieved.

この発明による半導体装置の製造方法は、シリ
コン単結晶層を選択エツチングした後、主表面全
体にシリコン薄膜を形成し、これを酸化処理して
酸化膜に変換することにより、素子のゲート耐圧
を上げ、高密度化を達成できると共に、高信頼性
を達成することができるという効果がある。
In the method of manufacturing a semiconductor device according to the present invention, after selectively etching a silicon single crystal layer, a silicon thin film is formed over the entire main surface, and this is oxidized to convert it into an oxide film, thereby increasing the gate breakdown voltage of the device. , it is possible to achieve high density as well as high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a〜dおよびe〜hは従来の半導体装置
の製造方法の一例および他例をそれぞれ工程順に
示す断面図、第2図a〜dはこの発明の一実施例
による半導体装置の製造方法を工程順に示す断面
図である。 201……サフアイヤ基板、202……シリコ
ン単結晶層、203……SiO2膜、204……シ
リコン薄膜、205……酸化膜。
FIGS. 1a to 1d and e to h are cross-sectional views showing one example and another example of a conventional semiconductor device manufacturing method in order of process, respectively, and FIGS. 2a to d are sectional views of a semiconductor device manufacturing method according to an embodiment of the present invention. FIG. 201...Sapphire substrate, 202...Silicon single crystal layer, 203...SiO 2 film, 204...Silicon thin film, 205...Oxide film.

Claims (1)

【特許請求の範囲】 1 サフアイヤ上のシリコン単結晶層上に耐シリ
コンエツチング材料からなるマスク層を選択的に
形成する工程と、前記マスク層で覆われないシリ
コン単結晶層をエツチングして前記サフアイヤを
露出させる工程と、前記マスク層を除去した後、
露出させたサフアイヤ上を含む主表面全面にシリ
コン薄膜を形成する工程と、このシリコン薄膜を
酸化処理して酸化膜に変換する工程とを含むこと
を特徴とする半導体装置の製造方法。 2 前記シリコン薄膜は多結晶シリコンである特
許請求の範囲第1項記載の半導体装置の製造方
法。 3 前記シリコン薄膜は非晶質シリコンである特
許請求の範囲第1項記載の半導体装置の製造方
法。 4 前記シリコン薄膜は予定酸化膜の厚さのほぼ
1/2以下の厚さに形成する特許請求の範囲第1項、
第2項、第3項のいずれかに記載の半導体装置の
製造方法。
[Scope of Claims] 1. A step of selectively forming a mask layer made of a silicon etching resistant material on a silicon single crystal layer on a sapphire, and etching the silicon single crystal layer not covered with the mask layer to remove the silicon single crystal layer on the sapphire. and after removing the mask layer,
A method for manufacturing a semiconductor device, comprising the steps of forming a silicon thin film over the entire main surface including the exposed sapphire, and converting the silicon thin film into an oxide film by oxidizing the silicon thin film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon thin film is polycrystalline silicon. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon thin film is amorphous silicon. 4. Claim 1, wherein the silicon thin film is formed to a thickness that is approximately 1/2 or less of the thickness of the intended oxide film,
The method for manufacturing a semiconductor device according to any one of Items 2 and 3.
JP56059749A 1981-04-22 1981-04-22 Manufacture of semiconductor device Granted JPS57176741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56059749A JPS57176741A (en) 1981-04-22 1981-04-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56059749A JPS57176741A (en) 1981-04-22 1981-04-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57176741A JPS57176741A (en) 1982-10-30
JPS6342862B2 true JPS6342862B2 (en) 1988-08-25

Family

ID=13122193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56059749A Granted JPS57176741A (en) 1981-04-22 1981-04-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57176741A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637317A (en) * 1990-04-11 1994-02-10 General Motors Corp <Gm> Thin-film transistor and its manufacture

Also Published As

Publication number Publication date
JPS57176741A (en) 1982-10-30

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