JPS6343033B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the generation of multiphase frequency signals in which each phase is fixed to each other in a particular phase relationship.

For example, FIG. 1 shows an example in which received signals from transducers Z ₁ to Z _p arranged at intervals d on a plane are combined to select a received signal in a specific direction θ. In FIG. 1, M ₁ to M _p indicate mixing circuits, in which each received signal of the oscillators Z ₁ to Z _p sent out from the preamplifiers B ₁ to B _p and the phase shifters D ₁ to D and the phase-shifted signal of the oscillator G sent from _p are separately combined. After the mixed outputs sent out from the mixing circuits _M1 to _Mp are added in an adder circuit A, a specific frequency signal is selected from the added outputs in a filter circuit F.
At this time, if the amount of phase shift is set so that the phase of the frequency signal sent out from each of the phase shifters _P1 to _Pp becomes a specific phase, the received signal in the specific direction θ is transmitted from the filter circuit F. can be extracted. Further, by changing the phase relationship of each frequency signal sent out from the phase shifters D ₁ to D _p to another phase shift relationship, the pointing direction θ can be arbitrarily changed. In this case, the phase shifters D ₁ to D _o can arbitrarily change the amount of phase shift within one frequency of the frequency signal, and the amount of phase shift of each phase shifter can be changed while maintaining the desired relationship. It is necessary to be able to control them in conjunction.
If such phase shifters D ₁ to D _p were constructed using ordinary circuit elements, the construction would be extremely complicated and expensive.

The present invention provides a device that can generate multiphase signals sent out from phase shifters D ₁ to D _p with a relatively simple configuration without using phase shifters as described above.

Examples of the present invention will be described below.

FIG. 2 shows an embodiment of the invention, in which 1 indicates a read-only memory. Here, for convenience of explanation, the read-only memory 1 includes 12-digit address terminals A0 to _A11 and 8-bit _output terminals ₀₁ to _08.
shall have the following.

Address terminals A ₀ to A ₁₁ designate storage addresses. Therefore, in the case of 12-digit address terminals, the read-only memory 1 has storage addresses up to 4096 addresses. Each memory address stores 8 bits of memory data, and each read bit of memory data is sent to each of the output terminals ₀₁ to ₀₈ . In addition, the address terminals A ₀ to A ₁₁ specify the memory address using a 12-digit binary number, and the number of each digit is assigned to the terminals A ₀ to A ₁ , A ₁ to A ₂ , A ₂ to A ₃ , and the other terminals. Carry is performed in the direction of the number.

Address terminals A ₀ to A ₁₁ of read-only memory 1
The respective numerical values of the counter 2 and the numerical value setter 3 are derived, and the storage address is designated by each numerical value. The counter 2 sends out a 7-digit binary count value, and the numerical value setter 3 sends out a 5-digit binary value. Then, the counted value of the counter 2 is sent to the lower seven digits A ₀ to A ₆ of the address terminal of the read-only memory 1, and the set value of the numerical value setter 3 is sent to the upper five digits A ₇ to A ₁₁ of the address terminal. Ru.

Therefore, since the read-only memory 1 has a 12-digit binary address terminal, it has 4096 memory addresses,
When the numerical value setter sequentially specifies numerical values from 0 to ²⁵ , ie, 32, storage addresses in the read-only memory 1 that differ by ²⁷ , ie, 128 addresses are sequentially specified.
Further, when the count value of the counter 2 changes from 0 to 127, the read-only memory 1 sequentially specifies 128 memory addresses based on the memory address j specified by the numerical value set by the numerical value setter 3.

The counter 2 counts the pulse train sent out from the frequency dividing circuit 4, and the counted value changes repeatedly from 0 to 127. The frequency dividing circuit 4 is a clock pulse source 5.
The pulse train is divided into 1/2 and sent.

Therefore, when the counter 2 counts the clock pulse train and the count value changes repeatedly from 0 to 127, the read-only memory 1 stores 128 adjacent memory addresses based on the address j specified by the numerical value setter 3. The 8-bit storage data specified and read out in sequence is sent to each of output terminals 0 ₁ to 0 ₈ .

In FIG. 3, pulse train a represents the pulse train of clock pulse source 5, and pulse train b represents pulse train a.
The pulse train of the frequency divider circuit 4 is shown in which the frequency is divided by, for example, 1/2. The pulse train b is sent to the counter 2, and the stored data at the storage address specified by the counted value is read out. When reading stored data, a high level output is sent out when the number is "1", and a low level output is sent out when the number is "0". Therefore, the divided pulse b
Each time the data is sent out, a level output corresponding to the stored data is sent out, as shown in FIG. ₃ d1 to _d8 . The storage outputs d ₁ to d ₈ are sent from the respective output terminals 0 ₁ to 0 ₈ to the respective latch circuits 6 ₁ to 6 ₈ . Here, the count value of the counter 2 changes at the rising edge of the input pulse b, and the stored data corresponding to the counted value is read out, but the stored data is read out after the memory address is specified, that is, at the rising edge of the pulse train b. It is transmitted with a delay of Δt.
This read delay Δt is caused by the characteristics of the storage element, and when high-level storage data is read out, it is sent out with a delay of Δt every time the pulse train b rises.

Latch circuits 6 ₁ to 6 ₈ are latch pulse generators 7
Based on the latch pulse of read-only memory 1
The output levels of output terminals 0 ₁ to 0 ₈ are latched.
That is _, the latch pulse generator 7 sends out the latch pulses shown in _FIG . The circuits ₆₁ to ₆₈ are latched.

Therefore, from each of the latch circuits ₆₁ to ₆₈ ,
Outputs corresponding to the read levels of the respective output terminals 0 ₁ to 0 ₈ of the read-only memory 1 are sent out, and the output terminals e ₁ to 0 8 in FIG.
As shown in _e8 , when the readout output of each output terminal ₀₁ to ₀₈ is at a high level for each readout, a high level latch output is maintained. Furthermore, when the output terminals 0 ₁ to 0 ₈ are at a low level each time they are read, a low level latch output is continuously sent out. Since the counter 2 repeats the counting operation every 128 pulses of the pulse train b, the latch output is also sent out repeatedly in accordance with the repetition of the counted value.

As mentioned above, each output of the latch circuits ₆₁ to ₆₈ is determined by the stored data at the memory address specified by the counter 2, and the same output is repeatedly sent out every time the counter 2 repeats counting. .

Therefore, when the count value of counter 2 repeatedly changes from "0" to "127", for example, among the memory addresses read out to output terminals _0-1 , the count value from "0" to "63" When the stored data at the memory address is written to "1" and the stored data at the memory addresses whose count value is from "64" to "127" is written to "0," the latch circuit b ₁ writes the data as shown in Figure 3. As shown in e ₁ , a high level rectangular wave is transmitted from the counter 2's count values "0" to "63" and a low level square wave from the count values "64" to "127".

As is clear from the above, the phase of this rectangular wave e ₁ can be arbitrarily changed by changing the write address of the stored data. Output end 0 ₂
If the stored data at each memory address that is read out is shifted by one address compared to the stored data at the memory address that is read out at the output terminal ₀₂ , the latch circuit ₆₂ outputs the data as shown in _FIG . Thus, a rectangular wave whose phase is delayed by one cycle of the pulse train b compared to the rectangular wave e ₁ is sent out. Similarly, the phase of the rectangular wave sent out from each of the latch circuits ₆₃ to ₆₈ is changed to the pulse train b.
It is possible to send out rectangular waves as shown in FIG. 3 e ₃ to e ₈ by sequentially delaying each cycle by one period. Further, the period of the rectangular waves e ₁ to e ₈ can be set to any period by changing the period of the pulse train b. Therefore, the period of the rectangular waves e ₁ to e ₈ is changed by the phase shifter D ₁ in FIG.
When used in accordance with each frequency signal of D p to D _p , the composite directivity direction of the receivers Z ₁ to Z _p can be set to the direction θ according to the phase shift of the rectangular waves e ₁ to e ₈ .

In FIG. 2, the counter 2 is connected to the address terminals A ₀ to A 11 of the read-only memory 1 and the bottom seven rows A ₀ to A ₁₁ .
A ₆ is specified, and the numerical value setter 3 specifies the upper five digit address terminals A ₇ to A ₁₁ . Therefore, when the set numerical value of the numerical value setter 3 is changed, data at a memory address different from the memory address from which the rectangular waves e ₁ to e ₈ were read is read out. Therefore, by appropriately setting the stored data at the memory address, the phase relationships of the rectangular wave sequences e ₁ to e ₈ in FIG. 3 can be arbitrarily set. Since the numerical value setter 3 sends out a 5-digit binary value, it is possible to designate 32 memory addresses.
Therefore, it is possible to change the phase relationships e ₁ to e ₈ in _FIG .
When used as each of the output waves of D p to D _p , the combined reception direction of the receivers Z ₁ to Z _p can be changed to 32 directions by changing the set numerical values of the numerical setting device 3 in Fig. 2. can. Note that in the above, the frequency signals sent out from the phase shifters D1 to _Dp in FIG. ₁ are sine waves or cosine waves, whereas the
In the figure, rectangular wave sequences e ₁ to e ₈ are generated and used, but no problem will occur if a filter is applied focusing on the fundamental wave components of the rectangular wave sequences e ₁ to e ₈ .

As described above, since the present invention generates a multiphase signal by reading out data stored in a read-only memory, it is possible to arbitrarily set the frequency and phase. Therefore, it is possible to obtain a multiphase frequency signal generation device suitable for use in forming a received beam as shown in FIG. In FIG. 1, the vibrators Z ₁ to Z _p are arranged in a straight line, but the vibrators are not limited to being arranged in a straight line, but can be arranged in a circle or any curved shape. That is, since any multiphase signal can be generated by reading the stored data, if the vibrators are arranged in a curved line, the phases of the multiphase signals may be arranged in a phase arrangement corresponding to the curved arrangement.

Further, the present invention can be used not only for forming a receiving beam as shown in FIG. 1 but also for forming a transmitting beam to obtain a suitable device. In other words, when forming a transmission beam, the excitation phase of each transducer may be set so that the ultrasonic waves transmitted from a plurality of ultrasonic transducers form equal-phase wavefronts in the desired direction. . Therefore, in this case, the multiphase signal may be made to match the resonant frequency of the vibrator, and the phase relationship between them may be set so as to form the equal phase wavefront. In addition, in FIG. 2, the read-only memory 1 is 4096
The storage circuit has 8 memory addresses, and each memory address has 8 bits of memory data, but the capacity of the memory circuit can be set as appropriate depending on the period of the frequency signal to be generated, the number of phase switches, etc. do it.

[Brief explanation of drawings]

FIG. 1 shows an example of an apparatus for forming an ultrasonic reception beam, FIG. 2 shows an embodiment of the invention, and FIG. 3 shows a waveform diagram for explaining its operation.

Claims (1)

[Scope of Claims] 1. A multiphase frequency signal generation device in which the phases of each of the multiphase frequency signals are switched in conjunction with each other, which has n memory addresses (n≧p×k), and each memory address is i. a memory circuit that sends out bits of memory data; a first address designation circuit that specifies one of the memory addresses 1 to n of the memory circuit determined for each P address interval; and a counting capacity P'. When a counter (P'≦P) is used and the counted value of the counter changes from 1 to P', the memory specified by the first memory address designation circuit among the memory addresses of the memory circuit Address j
From address j (j+p') based on (1≦j≦k)
a second address designation circuit that repeatedly designates up to an address according to the counting operation of the counter; and a clock pulse generation circuit that sends a clock pulse train to the counter of the second address designation circuit, When reading out the i-bit stored data by setting the period of the pulse train to 1/P' of the period of the multiphase frequency signal, an i-phase frequency signal is generated by using the data change of each bit as the phase data of the frequency signal. A multiphase frequency signal generation device characterized by: