JPS6343039B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a matrix display panel.

A matrix display panel has drive electrodes arranged in a matrix in both the X and Y directions and is used to display characters, graphs, or images. For example, in the case of a liquid crystal display, display is performed using (N×M) pixels formed by N data lines and M timing lines. At this time, multiplex driving is normally used in which one timing line is selected and data is written and driven from the data line to the pixels in that column, and the period during which data corresponding to one pixel is applied is 1/1/2 of the total. M, which is usually called duty.
Generally, 100 timing lines are required for image or graphical display.

FIG. 1 shows the drive electrode arrangement of a liquid crystal matrix panel. Data line S1 forming a drive electrode
.about.Sn are arranged, and the timing lines C1 to Cm constitute (n×m) pixels.

FIG. 2 is an example of the driving waveform of the panel in FIG. 1,
Since the timing lines C1, C2, . . . Cm are scanned, the duty becomes 1/m due to the m timing lines. In the case of image display, gradation is required, and gradation can be achieved by modulating the width of the driving pulse applied to the data line as shown in FIG. The problem with displaying television images using the raster scan method using such a drive system and panel is that in the case of a normal television signal, there are 525 scanning lines corresponding to the timing lines in one frame.
Also, the odd number field and even number field are each 262.5.
It is composed of interlaced books, so
If the image is displayed as it is, a drive with a duty of 1/262.5 will be required. Also, if the resolution is reduced to half, it will be necessary to drive at a duty of 1/131.25. However, with this driving duty, it is currently difficult to obtain sufficient contrast with liquid crystals. Therefore, it is necessary to equivalently lower the driving duty of the liquid crystal by some means and improve the contrast of the display to make the display body easier to view.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for driving a liquid crystal matrix panel in which the contrast can be improved.

The present invention increases the effective value ratio of ON/OFF applied to the liquid crystal by making the period in which no information is included before and after the vertical erase period in the video signal a state in which no voltage is applied to the liquid crystal. This improves contrast.

To explain the present invention in more detail, we will proceed based on a commonly used NTSC video signal as an example. Figure 3 shows the signal system, where signal A is the vertical synchronization signal VS, and B is the horizontal synchronization signal H.
-S and C are enlarged views, and D represents video signals V and S. Also, Figure 4 shows the horizontal synchronization signal in Figure 3 in an easy-to-understand manner, and the time of one field is 1/60 second, or 16.667 msec, and this includes 262.5 scanning lines. There is.
In the case of a liquid crystal matrix panel, it is possible to recognize images even with half this number of scanning lines, that is, 131, so if, for example, one out of every two scanning lines is thinned out and displayed, the drive will be equivalent to 1/131 duty. However, in reality, the image information is 200 to 262.5.
It is sufficient to display 220 lines; rather, the time corresponding to 40 to 60 lines, including the remaining vertical blanking period, often does not contain any information signals. Therefore, for example, if only the 20th to 240th scanning sections in Figure 4 display images, and 1 to 19 and 241 to 262.5 are pause periods, the number of timing lines on the panel will be
There will be 220 pieces. However, the line selection period of one timing line remains 1/131.25, but during the pause period, the potentials of the timing line and data line are kept the same so that the effective value is not applied to the liquid crystal display. Even during the selection period, the effective value ratio applied to the liquid crystal can be improved, and therefore the contrast can be improved.

Generally speaking, taking the V-NV voltage averaging method as an example, if the duty is 1/D, the effective value ratio when the liquid crystal is lit and when it is not lit, which is a measure of contrast, is On the other hand, the number of scanning lines allocated to the pause period is M
In the case of a book, by driving so that the effective value becomes 0 during the rest period, the effective value ratio becomes Therefore, the ratio of equation (2) is clearly larger than that of (1). For example, when N=10, D=131, and M=30, the ratio is 1.089 in the conventional case, but it increases to 1.104 in the driving method of the present invention, indicating that the contrast is improved.

FIG. 5 explains the drive waveform of the present invention, and represents the timing using the horizontal synchronizing signal H-S as a standard. One screen consists of one frame of odd and even fields, and one field is 1/60 second. For simplicity, odd and even fields are considered to be the same signal. Of the 262.5 scanning lines within one field period, m lines are used as the display period, and p lines and q lines near the vertical blanking period are set as rest periods. The timing lines C1 to Cm are sequentially scanned from C1 within the display period and end at Cm. At this time, amplitude-modulated display data is input to the data lines S1 to Sn. The amplitude of this data line is 2V ₀ in the voltage averaging method of V ₀ to NV ₀ . What is characteristic about this waveform is that the data line is in the rest period, and in odd frames in p and q.
The purpose is to set V _NSO to the same potential as V _NSE and the non-selection level of the timing line in even frames, so that no voltage is applied to the liquid crystal during the rest period, that is, to prevent the effective value from increasing during this period. Also, the frame signal f _L is
This is a basic signal for AC inversion drive for every odd-numbered frame and even-numbered frame.

FIG. 6 shows a drive circuit that generates a data signal to implement the drive method of this embodiment shown in FIG. Here, V _ONE is a voltage that sets the ON level of a data signal in an even field, and V _ONO is a voltage level that sets an ON level of a data signal in an odd field.
Also, V _OFFE is a voltage that sets the OFF level of the data signal in even fields, and V _OFFN
is the OFF of the data signal in the odd field
This is the voltage that sets the level. Furthermore, V _NSE is
The same voltage level as the non-select voltage level of the timing signal in the even field, V _NSO is
This is the same voltage level as the non-selection voltage level of the timing signal in the odd field. Here, according to the instruction of the frame signal _fL , the voltage selection circuit 10
selects the signal V _ONE or V _ONO for each field,
The voltage selection circuit 11 selects the signal V _OFFE or V _OFFO for each field and outputs it as V OFF.The voltage selection circuit selects the signal V _{NSE or} V _NSO for each field and outputs it as V _OFF . Output as _N.

Next, the voltage selection circuit 13 forms a signal of two voltage levels, the voltage V _ON and the voltage V _N , within the field according to the instruction of the pause period signal _fD . However, if the frame period is considered, there are four voltage levels.
Here, the period of the voltage V _ON is the period m shown in FIG. 5A, and the period of the voltage V _N is the period (p+q) shown in FIG. 5A. Further, the voltage selection circuit 14 creates a two-voltage level signal of the voltage V _OFF and the voltage V _N within one field according to the instruction of the pause period signal f _D . However, if the frame period is considered, there are four voltage levels. Here, the period of the voltage V _OFF is the period m shown in FIG. 5A, and the period of the voltage V _N is the period (p+q) shown in FIG. 5A. Here, the data signal level conversion circuit is a circuit that converts the AD-converted data signal Di into a liquid crystal drive level. That is, the voltage selection circuit 15 is different from the voltage selection circuit 1.
ON voltage level of output voltage V _ON ′ from 3
V _ONE or V _ONO is selected and output in accordance with the timing of the ON signal of the data signal Di. On the other hand, the voltage selection circuit 16 selects the OFF voltage level V _OFFE or V _OFFO of the output voltage V OFF _' from the voltage selection circuit 14.
is selected and output in accordance with the timing of the OFF signal of the data signal Di.

In this way, the voltage selection circuit 15 and the voltage selection circuit 1
The composite output signal Si from 6 will be supplied to any i-column electrode of a matrix display device, for example. Therefore, if there are n columns of data signal electrodes in a matrix display device, then n
data signal level conversion circuits 17 are required. The data signals Si to Sn thus formed are shown in FIG.

In this way, in this embodiment, the vertical blanking period and its vicinity (p+
In q), the timing line and the data line are maintained at the same potential _VN . Therefore, even if the liquid crystal is conventionally driven by the scanning lines of the entire screen including the scanning lines in the vicinity of these vertical blanking periods, for example, D lines, in this embodiment, The number of scanning lines near the vertical blanking period, e.g. M
By scanning the screen with a full screen scan line (D-M) book, except for books, substantially 1/2
The liquid crystal is driven with a duty of (DM). Therefore, compared to driving the liquid crystal with a conventional duty of 1/D, the effective value applied to the display increases, so that the contrast can be improved. This is because contrast is the effective voltage ratio
V _ON/OFF , which is completely dependent on the duty.

As described above, in the present invention, a plurality of data signal lines in the column direction and a plurality of timing signal lines in the row direction are arranged in a matrix, and the data lines have a pulse width proportional to the amplitude of an input video signal. A method for driving a matrix display panel in which a pulse signal is supplied, and the timing line is supplied with a horizontal synchronizing signal synchronized with a horizontal scanning signal of the input video signal. Since the erasure period includes a display pause period in which the input video signal is not supplied to the data signal line and the horizontal synchronization signal is not supplied to the timing signal line, the duty is reduced by the display pause period compared to the conventional duty. Since it can be driven with a duty ratio, the V _ON /V _OFF ratio of the display is improved accordingly, and therefore, a display with improved contrast can be realized.

[Brief explanation of the drawing]

FIG. 1 is a plan configuration diagram of a matrix display panel according to the present invention. FIG. 2 is a drive waveform diagram according to a conventional drive method. FIGS. 3A to 3D are signal waveform diagrams showing the relationship between the video signal input and the synchronization signal. FIG. 4 is a signal waveform diagram showing a horizontal synchronization signal of a video signal. FIGS. 5A to 5E are signal waveform diagrams showing drive waveforms in an embodiment of the present invention. FIG. 6 is a circuit block diagram showing an embodiment of the data signal forming circuit of the present invention. m...Display period, p, q...Display pause period, C1~
Cm...timing signal, Si...data signal, 10~
16...Voltage selection circuit.

Claims (1)

[Claims] 1. A plurality of data signal lines in the column direction and a plurality of timing signal lines in the row direction are arranged in a matrix, and the data lines have a pulse width proportional to the amplitude of the input video signal. A method for driving a matrix display panel in which a pulse signal is supplied, and the timing line is supplied with a horizontal synchronizing signal synchronized with a horizontal scanning signal of the input video signal. A method for driving a matrix display panel, comprising providing a display pause period in which the input video signal is not supplied to the data signal line and the horizontal synchronization signal is not supplied to the timing signal line during the erase period. 2. The matrix display panel according to claim 1, wherein during the display pause period, the potential of the timing signal line and the potential of the data signal line are maintained at the same potential. Driving method.