JPS6343840B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memories, in particular of the one-transistor dynamic type.

One-transistor dynamic type semiconductor memory is being put into practical use, for example, “IEEE
JOURNAL OF SOLID-STATE CIRCUITS,
VOL.SC−15, No.2, APRIL 1980 A64 kbit
MOS Dynamic RAM with Novel Memory
This type of semiconductor memory has a memory cell (consisting of one transistor and a paired capacitor) connected to one bit line BL, and a word line that turns on/off the transistor. WL, the other bit line paired with the one bit line BL, a dummy cell (consisting of a capacitor) connected to the bit line, and a dummy word line DWL connected to the capacitor (described later). Even in a typical semiconductor memory, a sense amplifier for discriminating between "1" and "0" is provided for each pair of bit lines BL, but the operation of this sense amplifier is different from BL,
If the potentials of BL and BL are close to each other, erroneous determination of "1" and "0" may be made. The main factor is power supply voltage fluctuation. If there is such a power supply voltage fluctuation, the charge level of the bit line BL will deviate from the specified value for reasons described later. As a result, erroneous data is read. However, such power supply voltage fluctuations are unavoidable, and it is necessary to take measures to prevent the reading of erroneous data.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to propose a one-transistor dynamic type semiconductor memory that can always read data correctly even when there are fluctuations in the power supply voltage.

In accordance with the above object, the present invention is characterized in that the other end of the capacitor in the dummy cell is directly charged from the potential of the bit line that charges one end of the capacitor.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram showing a general one-transistor dynamic type semiconductor memory to which the present invention is applied. In this figure, C ₁₁ and Q ₁₅ are a capacitor and a transistor that constitute a one-transistor dynamic type memory cell. "1" or "0" of the stored data is determined depending on whether or not the capacitor _C11 is charged. One end of transistor _Q15 is connected to bit line _BL1 , and the tip of bit line _BL1 reaches sense amplifier _SA1 . The word line WL to the bit line is tied to the gate of transistor _Q15 . A bit line ₁ is wired across the sense amplifier SA ₁ , and a dummy cell DC is provided at the tip of the bit line 1. A capacitor _C12 is provided in the dummy cell DC, and the other end is connected to the transistor _Q6 and the other end via the dummy word line DWL.
Tied to the intermediate connection point of Q ₇ . A dummy word line control signal DWL* is applied to the gate of transistor _Q7 . Similar configurations are formed over multiple stages, and the n-th stage is illustrated. In other words, it is a system centered around the sense amplifier SA _o .
Also, the pair of word line WL and dummy word line DWL is
In addition to this, multiple stages are formed, but they are not shown. The operation will be explained next.

2A and 2B are waveform diagrams used to explain the operation of the semiconductor memory shown in FIG.
Figure A is a waveform diagram for reading data "0", and Figure 2B is a waveform diagram for reading data "1". In FIG. 2A, before time _t1 , the bit line charge up signal BC is at the high potential power supply voltage.
Level above V _CC (more precisely V _CC + V _th + α,
(hereinafter referred to as V _CC *), and transistors Q ₁₁ , Q ₁₂ , Q _{6 ,} etc. in FIG. 1 are turned on. Here,
The bit lines BL and (corresponding to the general term BL ₁ . . . BL _o and ₁ . . . _o in FIG. 1) and the dummy word line DWL are charged to a high potential power supply voltage V _CC of, for example, 5V. Here, if the relevant bit line and word line are selected at time _t1 , the signal BC switches to the level of the low potential power supply voltage _VSS . Also, the word line WL goes to the V _CC * level, the dummy word line control signal DWL* goes to the V _CC level, and the dummy word line DWL goes to the V _SS level. The waveform diagram in FIG. 2A depicts reading data "0", so if we look at the memory cell (Q ₁₅ , C ₁₁ ), for example, the node N ₁₁
The potential of is approximately 0V. Therefore, word line WL
When the transistor Q ₁₅ turns on, the voltage charged on the bit line BL ₁ reaches the level of V _CC *.
The charge at V _CC flows into the capacitor C ₁₁ . This is why the potential of the bit line BL drops some time after time _t1 in FIG. 2A. The drop is indicated by ΔV _BL .

On the other hand, when looking at the dummy cell DC side, the time
Since the potential of the dummy word line DWL drops after _t1 , the potential of the bit line also drops via the capacitor _C12 . This decline is the second
It is indicated by ΔV _BL in Figure A. Here, a trial calculation will be made regarding the above ΔV _BL and the ΔV _BL . First, the capacity of the bit line (usually the same capacity for both BL and BL) is
Let C _BL be the capacitance of the memory cell capacitor C ₁₁ .
C _C11 and capacitor C ₁₂ in dummy cell DC
Let the capacity of C be _C12 . Normally, C _C12 is set to 1/2C _C11 . This is to ensure that reading by the sense amplifier SA ₁ can be performed smoothly in relation to the reference voltage described above. If the amount of charge absorbed by the capacitor _C11 from the bit line BL is Q _C11 , then Q _C11 ≒ V _BL × C _C11 = V _CC × C _C11 (1). Therefore, the voltage ΔV _BL becomes ΔV _BL =Q _C11 /C _BL =V _CC ×C _C11 /C _BL (2). Also, regarding the dummy cell DC, capacitor _C12 is connected to the dummy word line DWL (its voltage is
If Q _C12 is the amount of charge absorbed from V _DWL ), then Q _C12 ≒ V _DWL × C _C12 = V _CC × C _C12 …(3) Therefore, the voltage ΔV _BL is ΔV _BL = Q _C12 /C _BL =V _CC ×C _C12 /C _BL =1/2・V _CC ×C _C11 /C _BL …(4) From the above formulas (2) and (4), ΔV _BL =1/2ΔV _BL …(5) becomes. This differential voltage |ΔV _BL −1/2ΔV _BL | is later amplified by the sense amplifier SA. i.e.
When the LE (Latch Enable) signal (see Figure 2A) is applied to transistor _Q8 of Figure 1, the first
Transistors Q ₁₃ and Q ₁₄ in the figure become active and the differential voltage of the bit line BL, (above |ΔV _BL
−1/2ΔV _BL |). This situation is shown after time _t2 in FIG. 2A. Data is thus read from the sense amplifier (however, the read output line is not shown). A similar operation is performed when reading data "1", as illustrated in FIG. 2B. If the data is "1", the capacitor in the memory cell is charged (V _CC ), so the capacitor is connected from the bit line BL _1.
There is no charge transfer to _C11 , and the potential of bit line BL remains at V _CC as shown in FIG. 2B. The differential voltage of the bit line BL in this case is amplified after time _t2 in a state reversed from that in the case of FIG. 2A.

By the way, the problem is whether correct data "1" and "0" can always be read out even with the above-mentioned power supply voltage fluctuation (usually 4.5V to 5.5V).

FIG. 3 is a waveform diagram used to explain the operation when a power supply voltage fluctuation occurs in the semiconductor memory of FIG. 1, and the way to read the diagram is the same as that of FIGS. 2A and 2B. In this waveform diagram, power supply voltage fluctuations are illustrated as V' _CC and ΔV _CC , and particularly shows the case where the power supply voltage V _CC rises above V' _CC by ΔV _CC . What is particularly noteworthy here is the increase (the same applies to the case of decrease) in the power supply voltage V _CC ΔV _CC
On the other hand, the potential of the dummy word line DWL quickly follows and increases by ΔV _CC , whereas the potential of the bit line BL responds only extremely slowly. Due to this difference in reaction, (BL,
A voltage difference of ΔV occurs between BL) and DWL. Under such a state, if memory is selected (reading data "0") at time _t1 , a situation different from that shown in FIG. 2A will occur. In other words, the 2nd A
Comparing the potential of BL between t ₁ - _{t 2} in the figure and the potential of BL between t ₁ - _{t 2} in Fig. 3, we get
There will be a difference between the two. Here, as mentioned above, the operation of the sense amplifier SA for determining "1" and "0" is as follows.
Since it depends on the differential voltage of BL, BL,
If the potentials of the two are close to each other, erroneous determination of "1" and "0" may be made. If this is expressed numerically, the above-mentioned ΔV _BL and ΔV _BL are shown as follows. The amount of charge Q _C11 flowing into the capacitor C ₁₁ in the memory cell is Q _C11 ≒ V _BL × C _C11 = V′ _CC × C _C11 …(6), and ΔV _BL is ΔV _BL = Q _C11 /C _BL = V′ _CC ×C _C11 /C _BL …(7). Meanwhile, the capacitor _C12 in the dummy cell DC
The amount of charge Q _C12 flowing into this from the dummy word line DWL is Q _C12 = V _DWL × C _C12 = (V _CC + ΔV _CC ) × C _C12 (8), and ΔV _BL is ΔV _BL = Q _C12 /C _BL =V' _CC +ΔV _CC /C _BL ×C _C12 = 1/2・V' _CC +ΔV _CC /C _BL ×C _C11 (9). Therefore, by comparing equations (7) and (9) above, it can be seen that ΔV _BL includes an error equal to ΔV _CC . This error of ΔV _CC often leads to erroneous reading of data.

Therefore, the present invention uses some means to make both the potential of the dummy word line DWL and the potential of the bit line BL fluctuate in exactly the same step as the fluctuation of the power supply voltage, thereby generating the differential voltage ΔV shown in FIG. Try not to allow it.

FIG. 4 is a waveform diagram used to explain the operation within the semiconductor memory achieved by the present invention, and how to read it is the same as in FIGS. 2A, 2B, and 3. Now, even if the power supply voltage V _CC fluctuates (increases) in steps as shown in the figure before time t ₁ , DWL', BL,
BL becomes one and changes in exactly the same step. If this happens, the differential voltage ΔV in Figure 3
does not occur, and the voltage changes in exactly the same chart as shown in FIG. 2A after time _t1 . In other words, regardless of the presence or absence of power supply voltage fluctuations, the bit line BL,
The potential of BL will move on a fixed chart. This means that erroneous reading of data does not occur due to power supply voltage fluctuations.

FIG. 5 is a circuit diagram showing a semiconductor memory according to the present invention that can obtain the operating waveforms shown in FIG. 4. In this figure, the components labeled with the same reference symbols as in FIG. 1 are the same. Therefore, the configuration of dummy cell DC' is a particularly changed part. In this dummy cell DC′, the capacitor
C ₁₂ , C _o2 , etc. remain as before, but transistors Q ₁₆ , Q ₁₇ , transistors Q _o6 , Q _o7, etc. are added to each capacitor, and the dummy word line DWL in FIG. 1 is removed. This is why the dummy word line DWL is indicated as DWL′ in FIG. 4, and in reality, the node N ₁₂ in FIG.
, Nn ₂ , etc. becomes equivalent to the potential indicated by its DWL′. Further, the dummy word line control signal DWL* shown in FIG. 1 is commonly applied to the gates of new transistors Q ₁₇ , Q _o7 and the like. Furthermore, the first
The BC signal shown in the figure is also commonly applied to each gate of the new transistors Q ₁₆ , Q _o6 , etc. Note that the new transistors Q ₁₇ , Q _o7 , etc. are substantially equivalent to the transistor Q ₇ in FIG. In this case, attention must be paid to the functions of new transistors Q ₁₆ , Q _o6 , etc. Conventionally (see Figure 1), the other ends of capacitors C ₁₂ and C _o2 (each end is connected to bit wires ₁ and _o
In the present invention, instead _of supplying the power supply voltage V _CC to _{the bit line 1 (} connected _to
is supplied to the other ends of these capacitors C ₁₂ and _Co2 via transistors Q ₁₆ and Q _o6 . Then, the potential of nodes N ₁₂ and Nn ₂ (the potential of the conventional dummy word line DWL, that is, the potential corresponding to DWL′ in FIG. 4) is always the same as that of the bit lines ₁ ,
It moves in accordance with the potential of BL _o , and the generation of the undesirable voltage difference ΔV shown in FIG. 4 is not allowed. This way of thinking is possible because we focused on the fact that there is a large difference between the capacitance (parasitic capacitance) at nodes N ₁₂ and Nn ₂ and the capacitance (parasitic capacitance) attached to bit lines ₁ and _o . In other words, even if the power supply voltage V _CC fluctuates, the current flowing through the bit line is limited by Q ₁₁ and Q ₁₂ , and the capacitance of the bit line is large, so the potential of the bit line changes very slowly. On the other hand, since the node side capacitance is extremely small compared to the bit line capacitance, it can sufficiently follow very gradual changes in bit line potential. In this way, the bit line and nodes _N12 to _Nn2 have
No voltage difference occurs. Thus, as shown in Figure 4,
In particular, the DWL′ of the same step shown near time t ₁ ,
It is possible to realize the voltage transition of BL.

As described above, according to the present invention, a one-transistor dynamic type semiconductor memory is realized that can always read data correctly regardless of power supply voltage fluctuations.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a general one-transistor dynamic type semiconductor memory to which the present invention is applied, and FIGS. 2A and 2B are waveform diagrams used to explain the operation of the semiconductor memory shown in FIG. 1. , FIG. 3 is a waveform diagram used to explain the operation when power supply voltage fluctuation occurs in the semiconductor memory of FIG. 1, and FIG. 4 is a waveform diagram used to explain the operation in the semiconductor memory achieved by the present invention. FIG. 5 is a circuit diagram showing a semiconductor memory according to the present invention that can obtain the operating waveforms shown in FIG. 4. SA ₁ , SA _o ...Sense amplifier, BL ₁ , ₁ ...
A pair of bit lines, BL _o , _o ...Pair of bit lines, WL...Word line, DWL...Dummy word line, DWL*...Dummy word line control signal, DC,
DC′...Dummy cell, _Q16 , Q _o6 ...Transistor, _Q17 , Q _o7 ...Transistor, _C11 and _Q15 ...
...Capacitor and transistor that make up the memory cell, C _o1 and Q _o5 ... Capacitor and transistor that make up the memory cell, BC... Bit line charge up signal.

Claims (1)

[Claims] 1. A pair of bit lines connected to a sense amplifier;
A dummy cell including a memory cell connected to one of the pair of bit lines, a dummy cell including a capacitor connected in series to the other of the pair of bit lines, a word line that selects the memory cell together with the bit line, and the bit line. In a one-transistor dynamic semiconductor memory comprising a bit line charging circuit for charging a bit line, the dummy cell includes a first transistor connected across the capacitor, and a bit line charging circuit connected in series with the first transistor. and a second transistor that is connected and grounded, the first transistor is turned on at the timing when the pair of bit lines are charged to the power supply voltage, and the second transistor is connected to the dummy word corresponding to the word line. A semiconductor memory characterized by being turned on at the timing when a line control signal is sent.