JPS6343891B2 - - Google Patents
Info
- Publication number
- JPS6343891B2 JPS6343891B2 JP57117210A JP11721082A JPS6343891B2 JP S6343891 B2 JPS6343891 B2 JP S6343891B2 JP 57117210 A JP57117210 A JP 57117210A JP 11721082 A JP11721082 A JP 11721082A JP S6343891 B2 JPS6343891 B2 JP S6343891B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- film
- metal film
- forming
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は、たとえば、アルミニウム膜の微細加
工による配線の形成方法に関する。従来、アルミ
ニウム（Alと略す）配線は、フオトレジスト膜
を保護膜としてエツチするため、エツチ液、液
温、レジストとの密着性等により、同一幅のレジ
ストを用いても、均一に形成することは困難であ
り、しかも、段差部で断線する危険性があつた。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to, for example, a method for forming wiring by microfabrication of an aluminum film. Conventionally, aluminum (abbreviated as Al) wiring is etched using a photoresist film as a protective film, so it is difficult to form it uniformly even when using resist of the same width, depending on the etchant, liquid temperature, adhesion to the resist, etc. This was difficult, and there was a risk of wire breakage at the step.
本発明は、この点を改善したものであり、以下
説明する。第１図は、本発明による実施例の断面
図を示すものであり、先ず、同図ａに示すよう
に、半導体基板１の上にシリケートガラス
（NSG膜と略す）膜等の絶縁膜２を形成し、フオ
トレジストを保護膜として、ａの様な溝をあける
ものとする。引き続いて、同図ｂに示す様に、
NSG膜２上に、Al薄膜３を付着形成する。次に
Al蒸着膜３上に、低粘度のフオトレジストを、
スピンナにより塗布すると、図ｂ中の凹部に厚く
塗布されることになる。 The present invention improves this point, and will be explained below. FIG. 1 shows a cross-sectional view of an embodiment according to the present invention. First, as shown in FIG. A groove as shown in a is opened using photoresist as a protective film. Subsequently, as shown in Figure b,
An Al thin film 3 is deposited on the NSG film 2. next
A low viscosity photoresist is applied on the Al deposited film 3.
When applied using a spinner, a thick coating will be applied to the recesses shown in Figure b.
レジストを固化形成するため、プリベーク加熱
処理を十分行ない、レジストを現像処理すると、
第１図ｃの様に、Al配線３の凹部にレジスト４
が残る。続いて、Al膜３を化学的にウエツトエ
ツチング処理すると、第１図ｄに示す様に、Al
配線３は、NSG膜２の溝の周辺とレジスト４で
囲まれた部分のみ残る。 In order to solidify the resist, a sufficient pre-bake heat treatment is performed and the resist is developed.
As shown in Figure 1c, resist 4 is placed in the recessed part of Al wiring 3.
remains. Subsequently, when the Al film 3 is chemically wet-etched, the Al film 3 is wet-etched as shown in FIG. 1d.
For the wiring 3, only the portion around the groove of the NSG film 2 and the portion surrounded by the resist 4 remains.
この後、レジストを除去し、最終的に、図示し
ないが、これを被つてパシベイシヨン用絶縁膜を
推積することにより、配線形成は完成する。 Thereafter, the resist is removed, and finally, although not shown, a passivation insulating film is deposited over it to complete wiring formation.
本発明の実施例として、配線形成に於て、絶縁
膜２として、NSG膜の厚さ、２乃至3μmのもの
を用い、レジストパターンにより、幅1.0〜1.2μm
にて、深さ1.0μm程度の溝をあけるものとする。
このように形成することにより、第２図に示す
Al膜３を、過度にエツチして、例えば、このAl
膜が図中ｂ，ｃに点線で示す位置まで、エツチさ
れても、Al配線は、この規定の厚さ1.0μmより細
くなることはなく、一定のAl線幅を確保するこ
とができる。 As an embodiment of the present invention, in wiring formation, an NSG film with a thickness of 2 to 3 μm is used as the insulating film 2, and a width of 1.0 to 1.2 μm is determined by a resist pattern.
A groove with a depth of approximately 1.0 μm shall be made.
By forming in this way, the shape shown in Fig. 2 is obtained.
For example, if the Al film 3 is excessively etched,
Even if the film is etched to the positions indicated by the dotted lines b and c in the figure, the Al wiring will not become thinner than this specified thickness of 1.0 μm, and a constant Al line width can be ensured.
次に、本発明の別の実施例を第３図に示す。第
３図ａに、半導体基板１上に形成したSiO2等の
絶縁膜２を、例えば、反応性イオンエツチング法
などにより、電極接触用の孔６を形成する。引き
続いて同様のエツチング法により、異方性エツチ
ングを行なうことにより、第３図ｂに示すよう
に、孔６の形状を維持したまま絶縁膜２に細溝７
を形成する。この後、第１図ｂ〜ｄと同様の工程
を行なうことにより、電極及び微細配線を行なう
ことができる。この電極配線形成過程に於て、孔
６と溝７のエツヂ部分８を覆うアルミニウム配線
は、第１図で示したと同様に、レジストで凹部が
保護されるため、アルミニウム配線形成過程に於
るエツチング工程で断線を生じることはない。 Next, another embodiment of the present invention is shown in FIG. In FIG. 3a, holes 6 for electrode contact are formed in an insulating film 2 made of SiO 2 or the like formed on a semiconductor substrate 1 by, for example, reactive ion etching. Subsequently, by performing anisotropic etching using the same etching method, a narrow groove 7 is formed in the insulating film 2 while maintaining the shape of the hole 6, as shown in FIG. 3b.
form. Thereafter, electrodes and fine wiring can be formed by performing the same steps as in FIGS. 1b to 1d. In this process of forming the electrode wiring, the aluminum wiring covering the edge portion 8 of the hole 6 and the groove 7 is protected by a resist, so that the etching in the process of forming the aluminum wiring is protected as shown in FIG. No wire breakage occurs during the process.
また、本発明は、Si基板上にNSG膜あるいは
SiO2膜を形成した場合を例として説明したが、
この様な例に限られるものでなく、基板は多結晶
膜でも良く、また、NSG膜の代わりに、リンシ
リケートガラス（PSG）、ボロンシリケートガラ
ス（BSG）窒化膜（Si3N4）等上に溝を形成した
場合に於ても、同様に実施することができる。 In addition, the present invention provides an NSG film or
The case where a SiO 2 film was formed was explained as an example, but
The substrate is not limited to such an example, and the substrate may be a polycrystalline film, and instead of the NSG film, phosphorous silicate glass (PSG), boron silicate glass (BSG), nitride film (Si 3 N 4 ), etc. The same method can be applied even when a groove is formed in the groove.
第１図ａ〜ｄ，第２図、第３図ａ，ｂは、本発
明の実施例を適用した半導体装置の断面図であ
る。
１……半導体基板、２……NSG膜、３，５…
…アルミニウム膜、４……レジスト。
1a-d, 2, and 3a and 3b are cross-sectional views of a semiconductor device to which an embodiment of the present invention is applied. 1... Semiconductor substrate, 2... NSG film, 3, 5...
...Aluminum film, 4...Resist.
Claims (1)
絶縁膜に所定の深さの溝を形成する工程、前記溝
の深さよりも厚みが小さく選定された金属膜を絶
縁膜上に被着し、前記溝と相似形の溝部を有する
金属膜を形成する工程、表面全域にレジストを回
転塗布し、前記金属膜の溝部を埋める工程、塗布
されたレジストにプリベーク処理を施したのち現
像処理し、前記金属膜の溝部内のみレジストを残
す工程および、同一主面に露出する金属膜をエツ
チングし、絶縁膜の溝内に金属膜の配線を形成す
ることを特徴とする金属膜配線の形成方法。1 Forming an insulating film on a semiconductor substrate, and further forming a groove of a predetermined depth in the insulating film, and depositing a metal film selected to have a thickness smaller than the depth of the groove on the insulating film. , a step of forming a metal film having a groove portion similar to the groove, a step of spin-coating a resist over the entire surface and filling the groove portion of the metal film, a pre-baking treatment on the applied resist, and then a development treatment; A method for forming a metal film wiring, comprising: leaving a resist only in the groove of the metal film, etching the metal film exposed on the same main surface, and forming a metal film wiring in the groove of the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11721082A JPS598354A (en) | 1982-07-06 | 1982-07-06 | Formation of metal film wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11721082A JPS598354A (en) | 1982-07-06 | 1982-07-06 | Formation of metal film wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS598354A JPS598354A (en) | 1984-01-17 |
| JPS6343891B2 true JPS6343891B2 (en) | 1988-09-01 |
Family
ID=14706111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11721082A Granted JPS598354A (en) | 1982-07-06 | 1982-07-06 | Formation of metal film wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS598354A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62225341A (en) * | 1986-03-27 | 1987-10-03 | 住友金属工業株式会社 | Coated steel plate for bonding |
| CN101950748B (en) | 2005-01-28 | 2013-06-12 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| JP2010016240A (en) * | 2008-07-04 | 2010-01-21 | Panasonic Corp | Inductor and method of manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3841626A (en) * | 1973-03-01 | 1974-10-15 | Miller Printing Machinery Co | Sheet feeding apparatus |
-
1982
- 1982-07-06 JP JP11721082A patent/JPS598354A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS598354A (en) | 1984-01-17 |
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