JPS6343945B2 - - Google Patents
Info
- Publication number
- JPS6343945B2 JPS6343945B2 JP54122203A JP12220379A JPS6343945B2 JP S6343945 B2 JPS6343945 B2 JP S6343945B2 JP 54122203 A JP54122203 A JP 54122203A JP 12220379 A JP12220379 A JP 12220379A JP S6343945 B2 JPS6343945 B2 JP S6343945B2
- Authority
- JP
- Japan
- Prior art keywords
- black
- slice level
- resistor
- signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000007599 discharging Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000011084 recovery Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/403—Discrimination between the two tones in the picture signal of a two-tone original
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はフアクシミリにおける画信号の2値化
回路に関し、色地に書かれた原稿を読みとつた画
信号の黒色判別を行う際、地色に続く薄い黒の部
分をも確実と判別できる2値化回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit for binarizing image signals in facsimile, and when determining the black color of an image signal after reading an original written on a colored background, The present invention relates to a binarization circuit that can reliably discriminate even a thin black part following a .
第1図において1は地色に応じて白黒判別の基
準となるスライスレベルで、該スライスレベル1
と画信号2を比較することにより、スライスレベ
ル1より上位は白、ススライスレベル1より下位
は黒と判別し、画信号を白・黒の2値化信号3と
して送信するような2値化回路がある。
In FIG. 1, 1 is the slice level that is the standard for black and white discrimination according to the background color, and the slice level 1
By comparing the image signal 2 with the image signal 2, it is determined that the signal above slice level 1 is white and the signal below slice level 1 is black, and the image signal is transmitted as a binary signal 3 of white and black. There is a circuit.
即ち地色が濃い場合は当然スライスレベルを下
げてやらないと濃い色地そのものを黒と判別して
しまい、濃い色地上に書かれた文字又は線を黒と
判別しても、受信画は黒ベタとなつてしまい情報
を判読できない場合がある。 In other words, if the ground color is dark, unless you lower the slice level, the dark colored ground itself will be judged as black, and even if characters or lines written on the dark colored ground are judged to be black, the received image will be black. The information may become cluttered and unreadable.
そこで地色に応じてスライスレベルを変化させ
るスライスレベル決定回路を出願人は先に出願し
た。 Therefore, the applicant previously filed an application for a slice level determination circuit that changes the slice level according to the ground color.
即ち、第2図において抵抗r1,r2とコンデ
ンサC1及び設定値入力用ダイオード4からなる
クランプ回路5と積分器6によりスライスレベル
決定回路7が構成される。このような回路におい
て決定された2値化スライスレベル1と画信号2
が比較器8へ入力されて白・黒の判別がなされ
る。即ち第1図の如き画信号の2値化信号3が得
られる。 That is, in FIG. 2, a slice level determining circuit 7 is constituted by a clamp circuit 5 consisting of resistors r1 and r2, a capacitor C1, and a set value input diode 4, and an integrator 6. Binarization slice level 1 and image signal 2 determined in such a circuit
is input to the comparator 8 to determine whether it is white or black. That is, a binary signal 3 of the image signal as shown in FIG. 1 is obtained.
この時、スライスレベル1は画信号2が白から
黒への変化点において減少し、黒から白への変化
点において復帰する。即ち、変化点P1において
はコンデンサC1の放電によりレベルが下がり、
変化点P2においてはコンデンサC1に充電する
ことにより、復帰が行われる。今第2図における
抵抗r1,r2及びコンデンサC1による時定数
は一定値に決まる。即ち、コンデンサに充電する
時定数と放電する時定数が同じである場合、スラ
イスレベル1は第1図示の如く放電時P1と充電
時P2の傾き角θ1,θ2が等しくなる。従つて、
画信号2の途中にうすい黒の部分B,B1,B2
があつたとしてもB1位置ではスライスレベル1
より上位になり白と判別し、(B2位置では一部
分しか黒と判別せず黒信号の巾が減少してしま
う。
At this time, the slice level 1 decreases at the point where the image signal 2 changes from white to black, and returns at the point where the image signal 2 changes from black to white. That is, at the change point P1, the level decreases due to the discharge of the capacitor C1,
At the change point P2, recovery is performed by charging the capacitor C1. Now, the time constants due to the resistors r1 and r2 and the capacitor C1 in FIG. 2 are determined to be constant values. That is, when the time constant for charging the capacitor and the time constant for discharging the capacitor are the same, at slice level 1, the inclination angles θ1 and θ2 during discharging P1 and charging P2 are equal, as shown in the first diagram. Therefore,
Pale black parts B, B1, B2 in the middle of image signal 2
Even if there is heat, the slice level is 1 at the B1 position.
(At the B2 position, only a portion is determined as black, and the width of the black signal decreases.)
このような現象が生じると、例えば第3図イの
如き原稿9を送信しても縦線10の途中の文字情
報11の側方の線12が白地13側方の線14よ
り細く15書かれ、受信画16の美観を損うばか
りか、情報が不明確になる恐れがある。 When such a phenomenon occurs, for example, even if a document 9 as shown in FIG. , there is a risk that not only the aesthetic appearance of the received image 16 will be spoiled, but also that the information will become unclear.
本発明は上記欠点を解消するためになされたも
ので以下図面に従つて説明する。 The present invention has been made to solve the above-mentioned drawbacks, and will be described below with reference to the drawings.
第4図は本発明の実施例である2値化回路T1
を示す。
FIG. 4 shows a binarization circuit T1 which is an embodiment of the present invention.
shows.
即ち、第1の抵抗R1と、第2の抵抗R2と、
第3の抵抗R3と、第4の抵抗R4と、充電用ダ
イオードD1と、放電用ダイオードD2と、設定
値入力用ダイオードD3からなるクランプ回路1
7と、コンデンサC2および第5の抵抗R5から
なる積分回路18とによつてスライスレベル決定
回路19が構成され、画信号L1とスライスレベ
ル信号L2が比較器8に入力されて白・黒が判別
される。 That is, the first resistor R1, the second resistor R2,
Clamp circuit 1 consisting of a third resistor R3, a fourth resistor R4, a charging diode D1, a discharging diode D2, and a set value input diode D3
7, and an integrating circuit 18 consisting of a capacitor C2 and a fifth resistor R5 constitute a slice level determining circuit 19, and the image signal L1 and slice level signal L2 are input to a comparator 8 to discriminate between white and black. be done.
上記抵抗R1〜R4間の抵抗値の関係を
R2/R1=R4/R3 |R1,R2≫R3,R4
|
の如く抵抗R3,R4を抵抗R1,R2より小さ
くすることによつてダイオードD1を流れる電流
11はダイオードD2を流れる電流12より大と
なり、時定数も大きくなる。即ち、コンデンサC
2に充電する速さは放電する速さより充分速くな
り、スライスレベル信号の復帰が速くなり第5図
示に示すスライスレベルの特性曲線L3が得られ
る。 The relationship of the resistance values between the above resistors R1 to R4 is R2/R1=R4/R3 |R1,R2≫R3,R4
| By making the resistors R3 and R4 smaller than the resistors R1 and R2, the current 11 flowing through the diode D1 becomes larger than the current 12 flowing through the diode D2, and the time constant also becomes larger. That is, capacitor C
The speed of charging to 2 is sufficiently faster than the speed of discharging, and the slice level signal returns quickly, resulting in a slice level characteristic curve L3 shown in FIG.
従つて、上記スライスレベル決定回路19によ
るスライスレベル信号L3は第5図の如くなり、
画信号L1が黒から白への変化点ではコンデンサ
C2の放電は抵抗R1,R2を介して行われなだ
らかに降下し、一方黒から白への変化点において
はコンデンサC2の充電は抵抗R3,R4を介し
て行われる為速く充電され、立上り角θ3が小さく
なり復帰速度が速くなる。 Therefore, the slice level signal L3 from the slice level determining circuit 19 is as shown in FIG.
At the point where the image signal L1 changes from black to white, the capacitor C2 is discharged via the resistors R1 and R2 and gradually drops, while at the point where the image signal L1 changes from black to white, the capacitor C2 is charged through the resistors R3 and R4. Since the battery is charged quickly, the rising angle θ3 becomes smaller and the return speed becomes faster.
従つて黒から白への変化点において、スライス
レベルの立上りが速く十分ハイレベルに復帰でき
次のうすい黒の画信号B1,B2部においても黒
信号を取り出すことができ、上記スライスレベル
L2と画信号L1とによる2値化信号L3は画信
号L1の黒部を確実に黒として出力できる。 Therefore, at the point of change from black to white, the slice level rises quickly and returns to a sufficiently high level, and the black signal can be extracted even in the next faint black image signals B1 and B2, and the slice level L2 and the image The binary signal L3 based on the signal L1 can reliably output the black portion of the image signal L1 as black.
従つて、第3図の如く原稿を送信する場合、主
走査方向が矢印(X)の時、黒情報11に続く短
い白地に書かれた枠線12をも上記方法によつて
黒情報として判別することができ、従来では細線
15又は空白となつた枠線12を黒として2値化
信号化して送信することが可能となつた。 Therefore, when transmitting a document as shown in FIG. 3, when the main scanning direction is the arrow (X), the short frame line 12 drawn on a white background following the black information 11 is also determined as black information using the above method. It has become possible to convert the thin line 15 or blank frame line 12 into black and transmit the binary signal.
以上のように本発明ででは画信号の白黒を判別
する基準となるスライスレベルを画信号のレベル
によつて変化させると共に、画信号の黒から白へ
の変化点においてスライスレベルの復帰速度を画
信号の白から黒への変化点におけるスライスレベ
ル降下速度よりも速くするようにしたので、画信
号の黒部が続いたあとの白部において直ちにスラ
イスレベルを復帰でき、白部中のうすい黒部の画
信号レベルがスライスレベルより低くなるのでう
すい黒部をも黒として確実に2値化信号とするこ
とができ、原稿に忠実な2値化信号を送信するこ
とができ、受信側においても原稿通りの受信画を
得ることができ、情報の伝達が正確に行なえるも
のである。
As described above, in the present invention, the slice level, which is a reference for determining whether the image signal is black or white, is changed depending on the level of the image signal, and the recovery speed of the slice level is determined at the point where the image signal changes from black to white. Since the slice level is set to fall faster than the falling speed at the point where the signal changes from white to black, the slice level can be restored immediately in the white part after the black part of the image signal continues, and the thin black part in the white part can be quickly restored. Since the signal level is lower than the slice level, even faint black areas can be reliably converted into a binary signal as black, and a binary signal that is faithful to the original can be transmitted, and the receiving side can also receive the same as the original. images can be obtained and information can be transmitted accurately.
また、本発明では抵抗R1,R2,R3,R4
を所定の値に設定しダイオードD1,D2を互い
に逆方向に接続するという簡単な回路構成によつ
てスライスレベルの立上りと立下りの速度を切替
えることができ、また該レベルを一定値(Vref)
でクリツプしてあるので、該値(Vref)を適切
な電位に定めることによりスライスレベルの最下
限が画信号の黒ベタ部より常に上位にあるように
して該黒ベタ部を白と誤判定することのないもの
となつている。 Further, in the present invention, resistors R1, R2, R3, R4
The rise and fall speed of the slice level can be switched by a simple circuit configuration in which the diodes D1 and D2 are set to a predetermined value and the diodes D1 and D2 are connected in opposite directions, and the level is set to a constant value (Vref).
Since the value (Vref) is set to an appropriate potential, the lowest limit of the slice level is always higher than the black solid part of the image signal, and the black solid part is erroneously judged as white. It has become a thing of the past.
第1図は画信号とスライスレベルによつて得ら
れる2値化信号の説明図、第2図は第1図の2値
化信号を得る2値化回路図、第3図イは原稿の一
例を示す図、第3図ロは従来装置によつて受信さ
れた受信画の一例を示す図、第4図は本発明の実
施例を示す2値化回路図、第5図は同回路による
スライスレベルと画信号から2値化信号を得る説
明図である。
L1……画信号、L2……スライスレベル、L
3……2値化信号、T1……2値化回路、17…
…クランプ回路、18……積分回路、19,20
……スライスレベル決定回路。
Figure 1 is an explanatory diagram of a binary signal obtained from an image signal and slice level, Figure 2 is a diagram of a binary circuit that obtains the binary signal in Figure 1, and Figure 3 A is an example of a manuscript. 3B is a diagram showing an example of a received image received by a conventional device, FIG. 4 is a binarization circuit diagram showing an embodiment of the present invention, and FIG. 5 is a slice diagram using the same circuit. FIG. 3 is an explanatory diagram for obtaining a binarized signal from a level and an image signal. L1...Picture signal, L2...Slice level, L
3...Binarization signal, T1...Binarization circuit, 17...
...Clamp circuit, 18...Integrator circuit, 19, 20
...Slice level determination circuit.
Claims (1)
化する回路において、 上記画信号を、第1の抵抗R1と第2の抵抗R
2とからなる直列抵抗と、第3の抵抗R3と第4
の抵抗R4とからなる直列抵抗でそれぞれ分圧す
ると共に、分圧された各信号出力を互いに逆方向
に接続されたダイオードを介して共通のコンデン
サに接続し、かつ該コンデンサの放電出力を所定
電位でクリツプするダイオードを設け、 更に上記各抵抗の値をR2/R1=R4/R3
であつてR1,R2≫R3,R4の関係に設定し
たことを特徴とするフアクシミリにおける2値化
回路。[Claims] 1. In a circuit that binarizes an analog signal obtained by scanning a document, the image signal is passed through a first resistor R1 and a second resistor R1.
2, a third resistor R3 and a fourth resistor R3;
Each voltage is divided by a series resistor consisting of a resistor R4, and the divided signal outputs are connected to a common capacitor via diodes connected in opposite directions, and the discharge output of the capacitor is set at a predetermined potential. Provide a clipping diode, and further set the values of each of the above resistances to R2/R1=R4/R3.
A binarization circuit for a facsimile, characterized in that the relationship is set to R1, R2>>R3, R4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54122203A JPS5772469A (en) | 1979-09-21 | 1979-09-21 | Binary circuit in facsimile |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54122203A JPS5772469A (en) | 1979-09-21 | 1979-09-21 | Binary circuit in facsimile |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5772469A JPS5772469A (en) | 1982-05-06 |
| JPS6343945B2 true JPS6343945B2 (en) | 1988-09-01 |
Family
ID=14830101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54122203A Granted JPS5772469A (en) | 1979-09-21 | 1979-09-21 | Binary circuit in facsimile |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5772469A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145530U (en) * | 1988-03-15 | 1989-10-06 | ||
| JPH0522936U (en) * | 1991-04-12 | 1993-03-26 | デルタ工業株式会社 | Shift lock device for automobile chain lever |
-
1979
- 1979-09-21 JP JP54122203A patent/JPS5772469A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145530U (en) * | 1988-03-15 | 1989-10-06 | ||
| JPH0522936U (en) * | 1991-04-12 | 1993-03-26 | デルタ工業株式会社 | Shift lock device for automobile chain lever |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5772469A (en) | 1982-05-06 |
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