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JPS634396B2 - - Google Patents
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JPS634396B2 - - Google Patents

Info

Publication number
JPS634396B2
JPS634396B2 JP11518980A JP11518980A JPS634396B2 JP S634396 B2 JPS634396 B2 JP S634396B2 JP 11518980 A JP11518980 A JP 11518980A JP 11518980 A JP11518980 A JP 11518980A JP S634396 B2 JPS634396 B2 JP S634396B2
Authority
JP
Japan
Prior art keywords
incoming call
information
distribution
control processor
signal control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11518980A
Other languages
Japanese (ja)
Other versions
JPS5739690A (en
Inventor
Kenji Kataoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11518980A priority Critical patent/JPS5739690A/en
Publication of JPS5739690A publication Critical patent/JPS5739690A/en
Publication of JPS634396B2 publication Critical patent/JPS634396B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Description

【発明の詳細な説明】 本発明は分散制御方式の自動交換機における着
信呼分配制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an incoming call distribution control system in a distributed control automatic switching system.

従来集中制御方式の自動交換機では、システム
共通の一時記憶メモリを持ち、内線及びトランク
からの着信を検出すると、その着信呼情報をシス
テム共通一時記憶メモリに格納していた。このた
め内線及びトランクを増設する場合システムの共
通部分の増設を必らずともなつていた。また、シ
ステムに収容可能な最大回線数分の共通一時記憶
メモリを設けるとすると回線数の少ない程不経済
である。また従来の方式ではメモリ、及びメモリ
の書込、読出回路等に障害が起こつた場合には全
回線に影響を及ぼすなどの欠点があつた。
Conventional centralized control type automatic switching equipment has a system-common temporary storage memory, and when an incoming call from an extension or trunk is detected, the incoming call information is stored in the system-common temporary storage memory. For this reason, adding more extensions and trunks necessarily requires adding more common parts of the system. Furthermore, if common temporary storage memories are provided for the maximum number of lines that can be accommodated in the system, the smaller the number of lines, the more uneconomical it becomes. In addition, the conventional system has the disadvantage that if a failure occurs in the memory, memory writing/reading circuit, etc., it will affect all lines.

本発明の目的は上記の欠点を除去し、分散制御
方式に適した着信呼の分配制御方式を提供するこ
とにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an incoming call distribution control system suitable for a distributed control system.

本発明は交換機の内線、局線、専用線、局線中
継台の信号制御を行なう信号制御プロセツサ対応
に着信呼の着信検出をする手段と、着信呼情報の
記憶手段を有する一時記憶メモリと、局線中継台
からの着信呼分配要求操作を検出し着信呼情報の
分配を要求する手段とを設け、且つ接続制御プロ
セツサに対応して前記着信呼分配要求手段による
着信呼の分配要求を検出し着信呼情報を分配する
手段を設け、さらに情報転送バスに着信呼情報の
分配順序情報を記憶する手段を接続することによ
り、着信呼の分配制御を行なうため1つの信号制
御プロセツサに障害が起きても全回線に影響を及
ぼすことがない。また分配順序情報のみをシステ
ム共通の一時記憶メモリに設けることにより着信
呼の分配処理を信号制御プロセツサ毎に均等に行
なえる。また、前記一時記憶メモリ及びメモリの
書込、読出回路等に障害が発生した場合には接続
制御プロセツサにてあらかじめ決められた順序で
着信呼の分配を行なえばよい。従つて、回線数の
増設を簡単にし、障害に対して信頼性の高い自動
交換機の着信呼分配制御方式が得られる。
The present invention provides means for detecting incoming calls in response to a signal control processor that controls signals for extension lines, central office lines, dedicated lines, and central line relay boards of an exchange, and a temporary storage memory having means for storing incoming call information. means for detecting an incoming call distribution request operation from a central office line relay board and requesting distribution of incoming call information, and detecting an incoming call distribution request by the incoming call distribution requesting means in response to a connection control processor; By providing means for distributing incoming call information and further connecting means for storing distribution order information of incoming call information to the information transfer bus, it is possible to control the distribution of incoming calls even if one signal control processor fails. does not affect all lines. Further, by providing only the distribution order information in a temporary storage memory common to the system, the distribution processing of incoming calls can be performed equally for each signal control processor. Further, if a failure occurs in the temporary storage memory, memory writing/reading circuit, etc., the connection control processor may distribute incoming calls in a predetermined order. Therefore, it is possible to obtain an incoming call distribution control system for an automatic switching system that simplifies the expansion of the number of lines and is highly reliable against failures.

以下、本発明の実施例を図面を参照して説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の実施例のブロツク図である。
第2図は第1図に示す信号制御装置(プロセツサ
ー)のブロツク図路図、第3図は第1図に示す接
続制御装置(プロセツサ)のブロツク回路図、第
4図は第1図に示すシステム共通の一時記憶装置
である。
FIG. 1 is a block diagram of an embodiment of the invention.
Fig. 2 is a block diagram of the signal control device (processor) shown in Fig. 1, Fig. 3 is a block circuit diagram of the connection control device (processor) shown in Fig. 1, and Fig. 4 is a block diagram of the signal control device (processor) shown in Fig. 1. It is a temporary storage device common to the system.

第1図において、信号制御装置101には信号
制御プロセツサと信号制御を行なうためのプログ
ラムを記憶した固定メモリと制御の過程において
必要な情報を記憶する一時記憶メモリと信号制御
に関する装置を制御する制御回路とが含まれてい
る。又、接続制御装置102には接続制御プロセ
ツサと接続制御を行なうためのプログラムを記憶
した固定メモリと制御の過程において必要な情報
を記憶する一時記憶メモリと接続制御に関する装
置を制御する制御回路とが含まれている。
In FIG. 1, a signal control device 101 includes a signal control processor, a fixed memory that stores a program for signal control, a temporary memory that stores information necessary in the control process, and a control device that controls devices related to signal control. Contains a circuit. The connection control device 102 includes a connection control processor, a fixed memory that stores a program for connection control, a temporary storage memory that stores information necessary in the control process, and a control circuit that controls devices related to connection control. include.

まず、トランク108への着信、内線加入者1
07からの局線中継台扱者の呼出、局線中継台扱
者の再呼出を信号制御装置101で検出すると、
その着信した端末の収容位置情報および制御情報
等をバスインターフエース回路103と情報転送
バス105とバスインターフエース回路104と
を経て接続制御装置102に送出する。この接続
制御装置102では信号制御装置101から送ら
れてきた収容位置情報、制御情報等を第3図に示
す受信回路301にて受信し呼種情報、テナント
情報等の着信呼情報として必要な情報すべてを判
定回路302により決定したうえ、ラツチレジス
タ303に記憶しておき、上記、着信を検出した
信号制御装置101に送出回路304、バスイン
ターフエース回路104、情報転送バス105、
バスインターフエース回路103を経て返送す
る。一方信号制御装置101は上記着信呼情報を
信号制御プロセツサ対応に設けた一時記憶メモリ
110に格納する。尚、各端末が着信呼の分配を
される前に途中放棄により復旧した場合には、収
容位置情報により一時記憶メモリ110を検索し
その端末の着信呼情報を消去しておく。
First, an incoming call to trunk 108, extension subscriber 1
When the signal control device 101 detects the call of the office line relay stand operator from 07 and the re-call of the office line relay stand operator,
The accommodation position information, control information, etc. of the received terminal are sent to the connection control device 102 via the bus interface circuit 103, the information transfer bus 105, and the bus interface circuit 104. In this connection control device 102, accommodation position information, control information, etc. sent from the signal control device 101 are received by a receiving circuit 301 shown in FIG. 3, and necessary information as incoming call information such as call type information and tenant information is received. All are determined by the determination circuit 302 and stored in the latch register 303, and sent to the signal control device 101 that detected the incoming call by the sending circuit 304, bus interface circuit 104, information transfer bus 105,
It is returned via the bus interface circuit 103. On the other hand, the signal control device 101 stores the above-mentioned incoming call information in a temporary storage memory 110 provided corresponding to the signal control processor. If each terminal recovers due to abandonment before being distributed with incoming calls, the temporary storage memory 110 is searched based on accommodation position information and the incoming call information of that terminal is deleted.

また、局線中継台109の扱者が呼を扱つてい
る状態から空の状態になつたことを第2図に示す
電鍵情報受信回路201で検出した場合、又、連
続して空の状態であり一定時間を経過したことを
時計回路202にて検出した場合には、それぞれ
電鍵情報識別回路203、時間起動判定回路20
4にて判定し、着信呼分配要求情報を送信回路2
05、バスインターフエース回路103、情報転
送バス105、バスインターフエース回路104
を介して、接続制御装置102に送出する。接続
制御装置102ではバスインターフエース回路1
04、情報転送バス105、バスインターフエー
ス回路111を介してシステム共通一時記憶装置
112より分配順序情報を第4図に示す受信回路
401、メモリ読出回路403を介して一時記憶
メモリ405から読み出し送信回路404で返送
する。接続制御装置102ではその分配順序情報
に対応する信号制御装置101を介して一時記憶
メモリ110より着信呼情報を1つ読み出す。次
に読み出した着信呼を局線中継台109が扱うこ
とが可能かどうかを第3図に示す判定回路302
で判定し、可能であれば通話路106を制御して
着信した端末と局線中継台109を予約して局線
中継台109のランプ制御情報を受信回路20
6、ラツチレジスタ207を経て、ランプ制御回
路208に送り、局線中継台109に着信表示を
行なう。
In addition, when the telephone key information receiving circuit 201 shown in FIG. 2 detects that the telephone key information receiving circuit 201 shown in FIG. Yes, when the clock circuit 202 detects that a certain period of time has elapsed, the telephone key information identification circuit 203 and the time activation determination circuit 20 respectively
4, and transmits the incoming call distribution request information to the transmitting circuit 2.
05, bus interface circuit 103, information transfer bus 105, bus interface circuit 104
It is sent to the connection control device 102 via. In the connection control device 102, the bus interface circuit 1
04, the distribution order information is read out from the temporary storage memory 405 through the receiving circuit 401 and memory reading circuit 403 shown in FIG. Return with 404. The connection control device 102 reads one piece of incoming call information from the temporary storage memory 110 via the signal control device 101 corresponding to the distribution order information. Next, a determination circuit 302 shown in FIG. 3 determines whether the central line relay board 109 can handle the read incoming call.
If possible, control the communication path 106 to reserve the incoming terminal and the office line relay stand 109, and transmit the lamp control information of the office line relay stand 109 to the receiving circuit 20.
6. The signal is sent to the lamp control circuit 208 via the latch register 207, and an incoming call is displayed on the office line relay board 109.

一方、局線中継台109が扱うことが不可能な
場合には読み出した着信呼情報を一時記憶メモリ
110に戻して新しい別の着信呼情報を読み出
し、同様の処理を繰り返す。なお、1つの信号制
御装置で扱い可能な着信呼がない場合には信号制
御装置番号を更新して処理を繰り返す。1つの着
信呼分配処理が終わると接続制御装置102はバ
スインターフエース回路104、情報転送バスイ
ンターフエース回路111、第4図に示す受信回
路401を経てメモリ書込回路402において次
に処理する信号制御装置番号を一時記憶メモリ4
05に書き込んで記憶しておく。またバスインタ
ーフエース回路111、システム共通一時記憶装
置112に障害が発生した場合にはあらかじめ決
められた順序により分配制御を行なう。
On the other hand, if the central office line relay board 109 is unable to handle the call information, the read incoming call information is returned to the temporary storage memory 110, new and different incoming call information is read out, and the same process is repeated. Note that if there are no incoming calls that can be handled by one signal control device, the signal control device number is updated and the process is repeated. When one incoming call distribution process is completed, the connection control device 102 passes through the bus interface circuit 104, the information transfer bus interface circuit 111, and the receiving circuit 401 shown in FIG. Temporary storage memory 4 for device number
Write it in 05 and memorize it. Furthermore, if a failure occurs in the bus interface circuit 111 or the system common temporary storage device 112, distribution control is performed in a predetermined order.

以上本発明の1つの実施例について説明したが
第1図では通話路を接続して1つの交換機とみな
しているが通話路を分離して複数の交換機とみな
した場合にも本発明を適用できることは明白であ
る。また信号制御装置と接続制御装置をそれぞれ
1つずつ選んで説明したがそれぞれの装置が複数
ある場合も本発明は適用できることは明らかであ
る。尚、内線、局線、専用線、局線中継台の収容
は一例を示したものである。
One embodiment of the present invention has been described above, and although the communication paths are connected and considered as one exchange in FIG. 1, the present invention can also be applied when the communication paths are separated and considered as multiple exchanges. is obvious. Further, although one signal control device and one connection control device have been selected in the explanation, it is clear that the present invention can be applied even when there are a plurality of each device. Note that the accommodation of extension lines, office lines, dedicated lines, and office line relay boards is merely an example.

以上説明したように、本発明は信号制御プロセ
ツサ対応に設けた一時記憶メモリに着信呼情報を
記憶し、分配順序のみをシステム共通一時記憶装
置に設けたことにより、分散制御を行なつたうえ
着信呼の分配を均等に行うことができ、障害に強
く、信頼性の高い、自動交換機の着信呼分配制御
を実現する効果がある。
As explained above, the present invention stores incoming call information in a temporary storage memory provided corresponding to a signal control processor, and provides only the distribution order in a system common temporary storage device. This has the effect of realizing incoming call distribution control of an automatic switching system that can evenly distribute calls, is resistant to failures, and has high reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例のシステム構成図、第
2図は第1図に示す信号制御装置のブロツク回路
図、第3図は第1図に示す接続制御装置のブロツ
ク回路図、第4図は第1図に示すシステム共通一
時記憶装置のブロツク回路図である。 101……信号制御装置、102……接続制御
装置、103,104,111……バスインター
フエース回路、105……情報転送バス、106
……通話路、107……内線加入者、108……
トランク、109……局線中継台、110……一
時記憶メモリ、112……システム共通一時記憶
装置。
FIG. 1 is a system configuration diagram of an embodiment of the present invention, FIG. 2 is a block circuit diagram of the signal control device shown in FIG. 1, FIG. 3 is a block circuit diagram of the connection control device shown in FIG. 1, and FIG. This figure is a block circuit diagram of the system common temporary storage device shown in FIG. 1. 101... Signal control device, 102... Connection control device, 103, 104, 111... Bus interface circuit, 105... Information transfer bus, 106
...Call path, 107... Extension subscriber, 108...
Trunk, 109... Office line relay board, 110... Temporary storage memory, 112... System common temporary storage device.

Claims (1)

【特許請求の範囲】[Claims] 1 それぞれ通話路網に接続された内線と局線と
専用線と局線中継台とを含む端末の信号制御を行
なう少なくとも1つの信号制御プロセツサと、前
記端末相互の接続制御を行なう少なくとも1つの
接続制御プロセツサと、前記信号制御プロセツサ
と前記接続制御プロセツサとの間の情報転送を行
なう情報転送バスとを有する分散制御方式の自動
交換機における着信呼分配制御方式において、そ
れぞれ前記信号制御プロセツサに対応して設けら
れ前記自動交換機への着信を検出する着信検出手
段とこの着信の着信呼情報を一時記憶する一時記
憶手段と前記局線中継台からの着信呼分配要求操
作を検出し前記接続制御プロセツサにこの着信呼
情報の分配を要求する分配要求手段と、前記自動
交換機に共通に設けられ前記情報転送バスに接続
されるとともに前記着信呼情報の分配順序情報を
記憶する分配順序情報記憶手段と、それぞれ前記
接続制御プロセツサに対応して設けられ前記信号
制御プロセツサからの着信呼情報の分配要求を検
出する分配要求検出手段と前記分配順序情報記憶
手段から分配順序情報を読出す分配順序情報読出
手段と前記信号制御プロセツサから着信呼情報を
読出す着信呼情報読出手段と前記局線中継台に着
信呼を分配する着信呼分配手段とを備え、前記信
号制御プロセツサからの着信呼情報の分配要求を
検出するとき前記分配順序情報記憶手段の分配順
序情報に対応する信号制御プロセツサから着信呼
情報を読出し前記局線中継台に着信呼を分配する
ことを特徴とする着信呼分配制御方式。
1. At least one signal control processor that performs signal control of terminals including extension lines, central office lines, private lines, and central office line relay boards connected to the communication network, and at least one connection that performs mutual connection control between the terminals. In an incoming call distribution control method in a distributed control automatic switching system having a control processor and an information transfer bus for transferring information between the signal control processor and the connection control processor, An incoming call detecting means for detecting an incoming call to the automatic exchange; a temporary storage means for temporarily storing incoming call information of the incoming call; distribution request means for requesting distribution of incoming call information; distribution order information storage means provided commonly in the automatic exchange and connected to the information transfer bus and storing distribution order information of the incoming call information; distribution request detection means for detecting a distribution request for incoming call information from the signal control processor provided corresponding to the connection control processor; distribution order information reading means for reading distribution order information from the distribution order information storage means; When detecting a request for distribution of incoming call information from the signal control processor, the system comprises incoming call information reading means for reading incoming call information from the control processor and incoming call distribution means for distributing the incoming call to the central line relay stand. An incoming call distribution control system, characterized in that incoming call information is read from a signal control processor corresponding to the distribution order information of the distribution order information storage means and the incoming call is distributed to the central office line relay stand.
JP11518980A 1980-08-21 1980-08-21 Incoming call distribution control system Granted JPS5739690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11518980A JPS5739690A (en) 1980-08-21 1980-08-21 Incoming call distribution control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11518980A JPS5739690A (en) 1980-08-21 1980-08-21 Incoming call distribution control system

Publications (2)

Publication Number Publication Date
JPS5739690A JPS5739690A (en) 1982-03-04
JPS634396B2 true JPS634396B2 (en) 1988-01-28

Family

ID=14656549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11518980A Granted JPS5739690A (en) 1980-08-21 1980-08-21 Incoming call distribution control system

Country Status (1)

Country Link
JP (1) JPS5739690A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0351200U (en) * 1989-09-25 1991-05-17
JPH0383400U (en) * 1989-12-15 1991-08-23

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0671916B2 (en) * 1984-12-29 1994-09-14 島野工業株式会社 Bicycle dealer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0351200U (en) * 1989-09-25 1991-05-17
JPH0383400U (en) * 1989-12-15 1991-08-23

Also Published As

Publication number Publication date
JPS5739690A (en) 1982-03-04

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