JPS6346584B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a super high frequency transistor.

Due to the characteristics requirements of ultra-high frequency transistors, it is necessary to shorten the base-emitter distance and emitter width as well as to make the diffusion shallow. Therefore, polycrystalline silicon containing emitter impurities is used as a diffusion source.

However, in conventional manufacturing methods, when forming a base electrode in close proximity to the polycrystalline silicon layer, the two tend to come into complete contact or a state close to it, resulting in an E-B short or BV _EBO
The drawback was that deterioration and defects occurred frequently.

Hereinafter, a conventional manufacturing method will be explained with reference to FIG.

First, after forming a base region 2 and a graft base region 3 on a silicon substrate 1, an emitter impurity diffusion window 5 is opened in a silicon oxide film 4 formed on the surface of the substrate by a thermal oxidation method using a photolithography method. (Figure 1a).

Next, after forming polycrystalline silicon on the entire surface in advance,
A silicon oxide film is formed thereon by the CVD method (chemical vapor deposition method), and the CVD silicon oxide film is first patterned by photolithography, for example, by etching with an ammonium fluoride etchant using the resin film as a mask. , the patterned CVD
Using the silicon oxide film 7 as a mask, the polycrystalline silicon layer is selectively etched with a hydrofluoric acid or nitric acid etchant to form a polycrystalline silicon layer pattern 6 (first
Figure b).

Next, using the polycrystalline silicon layer 6 as a diffusion source,
While avoiding external diffusion with CVD silicon oxide film 7,
An emitter region 8 is formed by diffusing impurities into the silicon substrate 1 at high temperature for a certain period of time.

Next, in order to make an ohmic contact and form an extraction electrode, the CVD silicon oxide film 7 on the polycrystalline silicon layer 6 above the emitter impurity diffusion window is etched using a photolithographic method such as ammonium fluoride using the resin coating as a mask. An emitter contact window 9 is provided by etching with a base etchant. Next, a base contact window 10 is opened in the thermal silicon oxide film 4 on the graft base region 3 (the first
Figure c). Next, emitter lead electrodes 11 and base lead electrodes 12 are formed in required areas including above the emitter contact window 9 and base contact window 10, respectively (FIG. 1d).

However, in the conventional manufacturing method described above, the polycrystalline silicon layer 6 and the base extraction electrode 12 are very close to each other, and the side surfaces of the polycrystalline silicon layer 6 are exposed. If the base extraction electrode is formed to be shifted to the left or right, the two will immediately come into contact or nearly contact, resulting in E-B short or BV _EBO deterioration failure.

The present invention provides a method for manufacturing a semiconductor device that eliminates the drawbacks of the prior art described above.

The present invention prevents contact with the base electrode by coating the side surfaces of the polycrystalline silicon layer with a CVD silicon oxide film in advance.

The present invention will be explained below with reference to FIG.

A base region 2 and a graft base region 3 are formed on a silicon substrate 1, an emitter impurity diffusion window 5 is formed in a thermal silicon oxide film 4 on the surface of the substrate (FIG. 2a), and a window 5 is formed on the emitter impurity diffusion window 5. A polycrystalline silicon layer 6 containing impurities and a CVD silicon oxide film 7 for forming an emitter region are formed (second
Figure b). The above steps are the same as those of the conventional method.

Next, the entire surface of the substrate is covered with a CVD silicon oxide film 13 having a thickness of 3000 to 4000 Å, and the impurities in the polycrystalline silicon layer are diffused into the silicon substrate to form an emitter region 8. Next, CVD silicon oxide films 7 and 13 are formed on the polycrystalline silicon layer 6 to make ohmic contact and form an extraction electrode.
An emitter contact window 9 is formed in. Next, a thermal silicon oxide film 4 is formed on the graft base region 3.
Then, a base contact window 10 is opened in the CVD silicon oxide film 13 (FIG. 2c).

Next, emitter extraction electrodes 11 and base extraction electrodes 12 are formed in required areas including above the emitter contact windows 9 and base contact windows 10, respectively (FIG. 2d). The above electrode is, for example, Ti-Pt
-Although laminated metal electrodes such as Au or single-layer metal electrodes such as Al may be used, the former is often used in ultra-high frequency transistors from the standpoint of reliability.

According to the above method, since the side surfaces of the polycrystalline silicon layer 6 are covered in advance with the CVD silicon oxide film 13, even if the base extraction electrode 12 is shifted to the left or right due to manufacturing variations, the polycrystalline silicon layer 6 6 and the base extraction electrode 12 will never come into contact with each other.

Therefore, according to the present invention, EB shots and BV _EBO deterioration defects can be significantly reduced.

[Brief explanation of drawings]

FIGS. 1a, b, c and d are cross-sectional views for explaining a conventional manufacturing method, and FIGS. 2 a, b, c and d are cross-sectional views for explaining an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Base region, 3... Graft base region, 4... Silicon oxide film by thermal oxidation method, 5... Window for emitter impurity diffusion, 6... Polycrystalline silicon layer, 7... CVD silicon oxide film, 8... Emitter area, 9... Emitter contact window, 10...
Base contact window, 11...Emitter extraction electrode, 12...Base extraction electrode, 13...CVD silicon oxide film.

Claims (1)

[Claims] 1. A step of opening a window for diffusing emitter impurities in the silicon oxide film on the surface of the semiconductor substrate on which the base region has been formed, a step of forming a polycrystalline silicon layer containing an impurity for forming emitter impurities over the entire surface of the substrate, and a chemical vapor deposition method. A step of patterning the polycrystalline silicon layer by etching using the pattern of the silicon oxide film as a mask and leaving it in the window portion, and a step of patterning the polycrystalline silicon layer over the entire surface of the substrate including the side surfaces of the polycrystalline silicon layer by chemical vapor deposition. After coating with an oxide film, a step of diffusing impurities in the polycrystalline silicon layer into the substrate to form an emitter region, a step of opening contact windows for the emitter and base, and forming the emitter and base in the contact window. 1. A method of manufacturing a semiconductor device, comprising the step of forming an extraction electrode.