JPS6346979B2 - - Google Patents
Info
- Publication number
- JPS6346979B2 JPS6346979B2 JP6411980A JP6411980A JPS6346979B2 JP S6346979 B2 JPS6346979 B2 JP S6346979B2 JP 6411980 A JP6411980 A JP 6411980A JP 6411980 A JP6411980 A JP 6411980A JP S6346979 B2 JPS6346979 B2 JP S6346979B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- wiring
- layer
- polyimide resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 20
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims description 15
- 239000011574 phosphorus Substances 0.000 claims description 15
- 229920001721 polyimide Polymers 0.000 claims description 15
- 239000009719 polyimide resin Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 21
- 238000009792 diffusion process Methods 0.000 description 7
- 238000011109 contamination Methods 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
- C03C3/083—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
- C03C3/097—Glass compositions containing silica with 40% to 90% silica, by weight containing phosphorus, niobium or tantalum
Landscapes
- Chemical & Material Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geochemistry & Mineralogy (AREA)
- Materials Engineering (AREA)
- Organic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置における多層配線構造に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring structure in a semiconductor device.
AlゲートバイポーラMOSICにおいて、第１図
を参照し、Si基板１表面に厚いフイルドSiO2膜
２と薄いゲート用SiO2膜３を形成した上に第１
層のAl配線４やAlゲート５を形成するにあたつ
て、パツシベイシヨン用のリンを含むSiO2膜
（リンガラス）６をSiO2膜上に形成するが、MOS
の分極によるVTH（しきい電圧）の分極によるVTH
変動を防止するため及び、ゲートSiO2膜３形成
時にエミツタガラス（n+拡散用リンデポジツト
膜）からのリンのアウト・デイフイージヨン（外
部拡散）によるVTHのばらつきを防止するため
に、上記リンガラス膜６を薄く（100Å程度）か
つ低いリン濃度にしてあるのが普通である。 In an Al gate bipolar MOSIC, referring to FIG. 1, a thick field SiO 2 film 2 and a thin SiO 2 film 3 for gate are formed on the surface of a Si substrate 1, and then a
When forming the Al wiring 4 and Al gate 5 of the layer, an SiO 2 film (phosphorus glass) 6 containing phosphorus for passivation is formed on the SiO 2 film.
V TH due to polarization of V TH (threshold voltage)
In order to prevent variations in V TH due to out-diffusion of phosphorus from the emitter glass (phosphorus deposit film for n + diffusion) during formation of the gate SiO 2 film 3, the phosphorus glass film 6 is It is common to have a thin layer (about 100 Å) and a low phosphorus concentration.
ところでAl配線を多層化する場合にAl層の層
間絶縁膜としては回転塗布技術によつて表面平坦
化が実現でき、かつ耐熱性のあるポリイミド系樹
脂膜が適合し、リニア製品の多くに使用されてい
る。しかし、バイポーラMOSICの場合、MOS部
分で第１層のAl層の上に直ちにポリイミド系樹
脂（破線７で示す）を付けると、ポリイミド系樹
脂からの有機、無機の物質による汚染がゲート
SiO2膜を通して起り、半導体装置の特性が不安
定となつて信頼度が低下するおそれがあつた。 By the way, when multi-layering Al wiring, a polyimide resin film is suitable as the interlayer insulation film for the Al layer, which can achieve surface flattening by spin coating technology and is heat resistant, and is used in many linear products. ing. However, in the case of bipolar MOSIC, if polyimide resin (indicated by broken line 7) is immediately applied on top of the first Al layer in the MOS part, contamination by organic and inorganic substances from the polyimide resin will be gated.
This could occur through the SiO 2 film, making the characteristics of the semiconductor device unstable and reducing its reliability.
本発明は上記した問題点を取除くためになされ
たものであり、その目的は多層配線を有する半導
体装置の信頼度向上にある。 The present invention has been made to eliminate the above-mentioned problems, and its purpose is to improve the reliability of semiconductor devices having multilayer wiring.
この発明の内容を端的に言えば、第２図に示す
ようにSi基板１表面のSiO膜２，３上にリンを含
む薄いSiO2ガラス膜（リンガラス）６で覆い、
その上に第１層のAl配線４を形成し、この上に
リンを含む厚いSiO2ガラス膜（PSG）８で覆い、
その上をポリイミド樹脂膜７で覆つた上に第２層
のAl配線９を形成するものである。なお、必要
に応じて同図に示すように第２層のAl配線９を
覆うようにポリイミド樹脂膜１０を形成し、これ
を最終パツシベイシヨン膜とするか、あるいはさ
らにこの上に第３層のAl配線（図示しない）を
形成してもよい。 To put it simply, as shown in FIG. 2, the SiO films 2 and 3 on the surface of the Si substrate 1 are covered with a thin SiO 2 glass film (phosphorus glass) 6 containing phosphorus.
A first layer of Al wiring 4 is formed thereon, and covered with a thick SiO 2 glass film (PSG) 8 containing phosphorus.
A second layer of Al wiring 9 is formed on the polyimide resin film 7, which is then covered with a polyimide resin film 7. If necessary, as shown in the figure, a polyimide resin film 10 may be formed to cover the second layer Al wiring 9, and this may be used as the final passivation film, or a third layer Al wiring may be formed on top of this. Wiring (not shown) may also be formed.
このような多層配線構造においては表面SiO2
膜の上に形成した薄いリンガラス６によつて第１
層Al配線よりの汚染を防ぎ、一方、その上に形
成した厚いPSG膜８によつてポリイミド樹脂か
らの汚染を防ぐことになり、半導体装置の信頼度
が向上できる。 In such a multilayer wiring structure, the surface SiO 2
A thin phosphor glass 6 formed on the film allows the first
Contamination from the layered Al wiring is prevented, and on the other hand, the thick PSG film 8 formed thereon prevents contamination from the polyimide resin, thereby improving the reliability of the semiconductor device.
第３図ａ〜ｄは２層Al配線を有するAlゲート
バイポーラMOSICに本発明を適用した場合の実
施例における電極形成プロセスを示す。 FIGS. 3a to 3d show an electrode forming process in an embodiment in which the present invention is applied to an Al gate bipolar MOSIC having two layers of Al wiring.
(a) p-型Si基板（サブストレート）１１上に一部
でn+埋込層１２のための拡散を行ない、全面
にn-型エピダキシヤル層１３を成長させ、表
面SiO2膜１４をマスクとしてp+拡散アイソレ
ーシヨン層１５を形成し、これにより分離され
た領域をMOS部、領域をバイポーラ部と
して、領域にp+拡散ソース・ドレイン１６
を形成する一方、領域にp+拡散ベース１７
を形成する。(a) Diffusion for the n + buried layer 12 is performed on a part of the p - type Si substrate (substrate) 11, and an n - type epidaxial layer 13 is grown on the entire surface, and the surface SiO 2 film 14 is masked. A p + diffusion isolation layer 15 is formed as a p + diffusion isolation layer 15, and the separated region is used as a MOS part and the region as a bipolar part.
while forming a p + diffused base in the region 17
form.
(b) 領域側にリンのデポジツト拡散によりn+
エミツタ、コレクタコンタクト部１８，１９形
成しリンガラスを除去後領域側のゲート酸化
を行なつてゲートSiO2膜２０を形成し、この
後コンタクトホトエツチを行ない、この後リン
雰囲気拡散RPに通して全面にパツシベイシヨ
ン用リンガラス膜２１を厚さ100Å程度に形成
する。(b) n + due to phosphorus deposit diffusion on the region side
After forming the emitter and collector contact portions 18 and 19 and removing the phosphorus glass, gate oxidation is performed on the region side to form a gate SiO 2 film 20. After that, contact photoetching is performed, and after that, it is passed through a phosphorus atmosphere diffusion RP. A phosphor glass film 21 for passivation is formed on the entire surface to a thickness of about 100 Å.
(c) 全面にAlを蒸着し、パターニングエツチを
行なつてAlゲート２２及び第１層のAl配線２
３を形成する。(c) Al is deposited on the entire surface and patterned and etched to form the Al gate 22 and the first layer Al wiring 2.
form 3.
(d) 全面にCVD（気相化学デポジシヨン）法によ
り、リン酸化物（P2O5）を含むSiO2ガラス
（PSG）膜２４を5000〜10000Åの厚さに形成
し、次いでスピンオンによりポリイミド樹脂
（ポリイミド・イソインドロキナゾリンシオン）
膜２５を厚さ２〜4μｍ程度に形成する。この
後、必要部分にスルーホールエツチを行ない、
第２層Al配線２６を形成する。このようにし
てうすいリンガラス膜の上に第１層Al配線を
有し、その上に厚いPSG膜を介してポリイミ
ド樹膜の形成された多層構造を得る。(d) A SiO 2 glass (PSG) film 24 containing phosphorous oxide (P 2 O 5 ) is formed to a thickness of 5000 to 10000 Å on the entire surface by CVD (vapor phase chemical deposition), and then polyimide resin is deposited by spin-on. (Polyimide isoindoquinazoline)
The film 25 is formed to have a thickness of about 2 to 4 μm. After this, perform through-hole etching in the necessary areas,
A second layer Al wiring 26 is formed. In this way, a multilayer structure is obtained in which the first layer Al wiring is formed on a thin phosphorous glass film, and a polyimide resin film is formed thereon via a thick PSG film.
本発明は前記実施例に限定されず、これ以外の
種々の形態が考えられる。 The present invention is not limited to the above embodiments, and various other forms are possible.
本発明は少なくとも２層のAl配線を有し、一
部にMOS構造をもつ半導体装置全般に適用され
る。 The present invention is applicable to all semiconductor devices having at least two layers of Al wiring and partially having a MOS structure.
第１図は従来例を示す半導体装置の断面図、第
２図は本発明による半導体装置の断面図、第３図
ａ〜ｄは本発明の一実施例を示す半導体装置の製
造プロセスの工程断面図である。
１……Si基板、２……フイルドSiO2膜、３…
…ゲート用SiO2膜、４……Al配線、５……Alゲ
ート、６……リンガラス膜、７……ポリイミド樹
脂、８……PSG膜、９……第２層Al配線、１０
……ポリイミド樹脂、１１……p-Si基板、１２…
…n+埋込層、１３……n-エピタキシヤル層、１
４……表面SiO2膜、１５……p+アイソレーシヨ
ン、１６……p+ソース・ドレイン、１７……p+
ベース、１８……n+エミツタ、１９……n+コレ
クタコンタクト部、２０……ゲートSiO2膜、２
１……うすいリンガラス、２２……Alゲート、
２３……Al配線、２４……PSG膜、２５……ポ
リイミド樹脂、２６……第２層Al配線。
FIG. 1 is a cross-sectional view of a semiconductor device showing a conventional example, FIG. 2 is a cross-sectional view of a semiconductor device according to the present invention, and FIGS. It is a diagram. 1...Si substrate, 2...Field SiO 2 film, 3...
... SiO 2 film for gate, 4 ... Al wiring, 5 ... Al gate, 6 ... Phosphorous glass film, 7 ... Polyimide resin, 8 ... PSG film, 9 ... Second layer Al wiring, 10
...Polyimide resin, 11...p - Si substrate, 12...
...n + buried layer, 13...n - epitaxial layer, 1
4...Surface SiO 2 film, 15...p + isolation, 16...p + source/drain, 17...p +
Base, 18...n + emitter, 19...n + collector contact part, 20... gate SiO 2 film, 2
1...Thin phosphorus glass, 22...Al gate,
23... Al wiring, 24... PSG film, 25... Polyimide resin, 26... Second layer Al wiring.
Claims (1)
有する半導体装置であつて、上記SiO2膜上にリ
ンを含むSiO2ガラス膜を介してAlよりなる第１
層配線が形成され、この第１層配線上にリンを含
むSiO2ガラス膜を介してポリイミド系樹脂膜が
覆われ、そのポリイミド樹脂膜上に第２層配線が
形成されていることを特徴とする半導体装置。1 A semiconductor device having multilayer wiring on a SiO 2 film on the surface of a semiconductor substrate, wherein a first layer made of Al is placed on the SiO 2 film via an SiO 2 glass film containing phosphorus.
A layer wiring is formed, a polyimide resin film is covered on the first layer wiring via a SiO 2 glass film containing phosphorus, and a second layer wiring is formed on the polyimide resin film. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6411980A JPS56161655A (en) | 1980-05-16 | 1980-05-16 | Multilayer aluminum wiring for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6411980A JPS56161655A (en) | 1980-05-16 | 1980-05-16 | Multilayer aluminum wiring for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56161655A JPS56161655A (en) | 1981-12-12 |
| JPS6346979B2 true JPS6346979B2 (en) | 1988-09-20 |
Family
ID=13248851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6411980A Granted JPS56161655A (en) | 1980-05-16 | 1980-05-16 | Multilayer aluminum wiring for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56161655A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197846A (en) * | 1982-05-14 | 1983-11-17 | Oki Electric Ind Co Ltd | Manufacture of multilayer wiring structure |
| JPS59117236A (en) * | 1982-12-24 | 1984-07-06 | Hitachi Ltd | semiconductor equipment |
-
1980
- 1980-05-16 JP JP6411980A patent/JPS56161655A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56161655A (en) | 1981-12-12 |
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