JPS6347020B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division multiplexing system in which different speed data terminals are mixedly accommodated in a time division multiplexing device or a time division switch, and in particular to changing the accommodation status of different speed data terminals and changing the accommodation status between switching centers. The aim is to easily change the assignment of speed types of interoffice lines to be used, and to easily set and identify speed groups on the multiplexing device or exchange side.

Conventionally, the assignment of speed types of data terminals in multiplex transmission lines and subscriber lines between multiplexers or stations has been fixed. For this reason, when not only traffic demand but also the distribution of terminal speeds fluctuates temporally and geographically, no system has been established that allows the network to automatically deal with these fluctuations. In order to economically realize a data exchange network, it has been pointed out that it is necessary to establish a flexible method for accommodating groups of data terminals with different speeds and for effectively using lines between stations. It's here.

Conventionally, terminals with various speeds were accommodated at multiplex channel positions fixedly determined by each speed, as shown in FIG. In Fig. 1, the in-home line terminating device 2 applies an envelope to the data and control line information sent from the terminal 1. Normally, for 6 or 8 bits of data, the F bit for synchronization and the F bit for status display are applied. At the same time, it is assembled into a signal with the S bit added, and at the same time, it is converted into a bipolar signal matching the subscriber line signal level and sent to the subscriber line 3. The home line termination device 2 also performs reverse conversion on the data from the subscriber line 3 and sends it to the terminal 1. A bipolar signal on the subscriber line 3 is converted into a unipolar signal by an in-office line termination device 4, and the unipolar signal is multiplexed by a multiplexer 5.

Different types of in-home line termination equipment 2 and in-office line termination equipment 4 are installed for each speed type of terminals to be accommodated, and if the subscriber side has multiple input/output devices with different speeds, Correspondingly, each device 2,
4 had to be installed on the network side for each speed. It should be noted that in the past, the F bit used when assembling an envelope was a simple pattern, for example, 101010, and was used only for octet synchronization. Conventionally, in a multiplexing office or switching office, the housing location of a terminal has been determined in advance according to the data rate of the terminal. Therefore, when changing the terminal speed, it is necessary to relocate the terminal to a channel position that is optimally designed for the data of the new speed, specifically, to a location where the in-office line termination equipment is accommodated that corresponds to the relevant speed. The drawback was that I had to do it.

FIG. 2 shows a configuration diagram when the output of the multiplexing device 5 is connected to the intra-office line termination device 7 connected to the exchange 8 using the multiplexing circuit 6. In FIG. In FIG. 2, a terminal accommodation group 1 accommodates a plurality of terminals 1 and multiplexes data sent from each terminal and provides it to the network side.
0 and 11 are provided. Previously, terminal housing group 1
0 or 11 had an accommodation configuration in which each terminal within the group was limited to those with the same transport speed (bearer rate). For example, if the multiplex line speed of the multiplex line 6 is 64 Kb/s, this 64 Kb/s
The bearer rate of each terminal within terminal accommodation group 10 was unified to 3.2 Kb/s within terminal accommodation group 11, and the bearer rate of each terminal was unified to 12.8 Kb/s within terminal accommodation group 11. . In order to change this pre-assigned bearer rate, contact the switching center in advance, change the subscriber information indicating the correspondence between each channel and subscriber, and change the information on each channel and memory used for processing within the switching center 8. There was the complexity of having to change the correspondence relationship between the two, or in other words, change the accommodation. Here, the channel refers to a group of 24 speeds in units of 64 Kb/s, assuming a PCM-24 transmission line of 1.5 Mb/s, for example. Also, even on the inter-office line 9, a speed type is fixedly assigned to each inter-office line, regardless of traffic fluctuations depending on speed, that is, even if traffic is concentrated on a line with a certain bearer rate. There was no proper way to use interoffice lines.

The object of this invention is to allocate an F-bit pattern corresponding to the channel speed to the synchronization bit (F-bit) in one frame on a multiplex transmission path, and to determine the speed type based on the F-bit pattern on the multiplexer or exchange side. The purpose is to make it possible to identify each other and to realize efficient use of multiple transmission lines or subscriber system equipment.

FIG. 3 shows an embodiment of this invention, with symbols 1,
Reference numerals 2, 3, 4, and 5 designate the same devices as the corresponding ones described in FIGS. 1 and 2. In this example, F
A pattern generation circuit 14 is provided, which is connected to the multiplexing device 5 and generates F-bit patterns individually assigned to each terminal according to the multiplexing order and speed type when multiplexing terminals of various speeds. do.
The F-bit pattern insertion circuit 15 from this F-pattern generation circuit 14 inserts the F-bit pattern into the multiplexed data and sends it out onto the multiplex line 6 or the inter-office line 9.

That is, various F bit patterns are generated by the F bit pattern generation circuit 14 in accordance with various bearer rates of terminal data accommodated in the terminal accommodation groups 12 and 13 and differences in accommodation positions corresponding to the bearer rates, that is, accommodation methods. The signal is inserted by the insertion circuit 15 and sent out onto the multiplex transmission path. Therefore, these various F
If the switching center 8 side has bit pattern identification means, it will be possible to easily deal with changes in the bearer rates handled by a terminal accommodation group, the mixing ratio of different bearer rates, the mixing order, the accommodation method, etc.

For example, the F bit pattern in the multiplexed data as shown in FIG. 4A is 9.6 Kb/s, 4.8 Kb/s,
s, for each terminal with a terminal speed of 2.4 Kb/s, that is, the transmission speed of each terminal is 12.8 Kb/s,
For example, patterns shown in FIG. 4B, C, and D are assigned to bearer rates of 6.4 Kb/s and 3.2 Kb/s, respectively. In this case, as shown in Figure 4, if the higher the speed, the shorter the pattern period is assigned.
Since synchronization detection can be performed quickly, the higher the speed, the faster synchronization can be established.

It is also possible to accommodate terminals with different speeds in the same terminal accommodation group as F-bit patterns, and to assign patterns to each individual terminal in accordance with the speed mixture ratio and multiplexing order of the accommodated terminals. In this case, the speed mixing ratio and multiplexing order are determined in advance. Also, regarding the speed-based allocation method for the inter-office line 9, if the F-pattern generation circuit 14 and F-pattern insertion circuit 15 are used, speed type changes can be communicated to the opposing station using a common line signal even in response to speed-based traffic fluctuations. It is possible to notify in inches without having to do so.

Assuming a terminal accommodation configuration as shown in FIG. 3, which shows an embodiment of the present invention, it is necessary for the switching center to constantly identify the speed type of the terminal using the F bit on the subscriber line. An example of the implementation means is shown below. The switching center must have a synchronization device to perform frame synchronization for each subscriber line and to identify terminal speeds. A block diagram of the terminal speed identification block in the synchronization device is shown in FIG.
For example, the memory area 16 stores multiple line speeds.
F for synchronization used in a 64Kb/s channel
A memory field is provided in which bits are stored.

The memory area 16 stores in advance the information of the F bit of each channel transmitted through the multiplexed line up to the relevant point in time, and this information content is stored in advance for each channel that is input to the exchange side at the same time. It is read out in synchronization with the latest F bit and stored in the shift register 17. The information stored in the shift register 17 is shifted one bit to the right according to the octet clock output from the terminal 21 at each channel break, and then stored at the same address in the memory area 16. Ru. (The latest F bit information is added and the oldest F bit information is deleted.) When an F bit pattern with a bearer rate of 12.8 Kb/s is input, its 5 bits (10011) A match is detected in the AND circuit 31, and the flip-flop 32 is set. bearer rate
In the case of 4.8 Kb/s, when (01011) in the F bit pattern is input, a match is detected in the AND circuit 33, and the output from the AND circuit 34 is generated by the output of the output, the output of the flip-flop 32, and the clock, and the output is output from the flip-flop. 35 is set.
When an F bit pattern with a bearer rate of 3.2 Kb/s is input, a match is detected by AND circuits 36 and 37 using (00011) and (11011), and the output is ANDed by the output of flip-flop 35 and the clock. An output is obtained from circuit 38. In this way, the pattern detection circuit 18 detects which of the F bit patterns shown in FIG. 4 the F bit pattern in the shift register 17 matches, and the encoder 19 encodes the result. is reported to the call processing program. Here, when the three input signal lines from the top to the third in the encoder 19 are (100), the bearer rate is 12.8Kb/s,
(010), the bearer rate is 6.4Kb/s,
(001) corresponds to a bearer rate of 3.2 Kb/s.

Based on the output of the encoder 19 and the conditions for establishing synchronization, the program can identify the change state of the joining I/D speed information.

Also, the F bit pattern matching result is simultaneously output to terminal 2.
2 to a synchronization protection circuit (not shown);
The fact that synchronization protection is provided for each multiplex line is similar to the principle of known synchronization devices.

Further, the F bit pattern entered into the shift register 17 is shifted by one bit and then stored again in the portion corresponding to the corresponding line in the memory area 16 for synchronous calculation. The reason for shifting one bit at a time is that the F bits that are transmitted one after another are sequentially stored in memory according to channel correspondence, and then the 9-bit F bit pattern in the memory area 16 that was received just before and the latest F bit are stored. This is because it is necessary to determine on a case-by-case basis which pattern the F bit pattern, together with the F bit pattern, matches with the pattern assumed within the station.

However, it is assumed that the pattern detection circuit 18 operates based on the various clocks shown in FIG.
The clocks of the pattern detection circuit correspond to D, E, and F in Figure 6, the clocks are generated every fifth octet clock, the clock has a period twice that of the clock, and the clock has a period four times that of the clock. It is a cycle. From the octet clock shown in FIG. 6B (FIG. 6C simply corresponds to a reduced length on the time axis) that coincides with each F bit in the multiplexed data clock shown in FIG. 6A, Corresponding to the F bit pattern shown in FIG. 4, the 1st F bit _F1 , which is the beginning of the entire pattern period, has the pattern shown in FIG.
As shown in E and F, respectively, the clock, ,
The 6th F bit, which generates a clock in any of
At _F6 , only the clock is generated, and at the 11th F bit _F11 , which is the beginning of the intermediate cycle F bit pattern and the shortest cycle F bit pattern, a clock is generated at the clock. Such a clock, , is connected to terminals 23 and 2 in Fig. 5.
4 and 25 to the pattern detection circuit 18, and each clock, , is supplied to the pattern detection circuit 18, respectively.
Used for pattern detection of bearer rates of 12.8Kb/s, 6.4Kb/s, and 3.2Kb/s.

The configuration for identifying the data rate on multiple lines shown in Figure 5 can be configured in almost the same format even if the number of F-bit patterns used increases significantly, provided a separate detection circuit is provided for each pattern. This can be realized with the following circuit.

Further, in FIG. 1, if the present invention is applied to the case where terminals having a plurality of speed types are switched and used, the configuration shown in FIG. 8 can be realized. Terminals 1 having various speeds are connected to the subscriber line 3 by being switched by a selection circuit 20. At this time, for example, a signal with a bearer rate of 12.8 Kb/s as shown in FIG. 7A is converted into a 64 Kb/s universal signal as shown in FIG.
By doubling the bit rate to 64Kb/s and at the same time reconfiguring it into a signal format that repeatedly generates 5 identical octets, we have added the ability to create a universal signal for data at any speed. The line termination device 2 is provided with a 64Kb
All you need to do is prepare one for universal signals of s speed.

What is important here is that it is only necessary to assume one type of in-home line termination device 2 and in-office line termination device 4, and in the conventional configuration method, various different interfaces are installed at the exchange center depending on the types of terminals accommodated. This means that the economical efficiency of the exchange can be greatly improved compared to the case where it would have been necessary to install it on the side.

As explained above, according to the present invention, in a time division multiplexing system that accommodates a mixture of data terminals of different speeds, when a condition arises to change the terminal speed within a group of accommodated terminals, or when terminals of various speeds are switched and used. When changing the usage speed type of the inter-office line, it is possible to change the allocation by speed of the inter-office line without changing the accommodation location of the terminal on the network side, and to change the allocation by speed of the inter-office line to the other station using the common line. without notice,
This problem can be dealt with simply by identifying the type of F bit pattern.

Also, when switching between terminal devices,
By unifying data on subscriber lines to a 64Kb/s universal signal, the type of in-house line termination equipment and in-office line termination equipment can be limited to just one type.
It becomes possible to improve economic efficiency. By individually assigning an F bit pattern to each speed type determined by the storage location classification, the network side can
Only a small amount of memory and logic circuits are required to identify the bit pattern, and the economic effects of this invention can be expected to be very large.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams of conventional terminal accommodation for various speeds, FIG. 3 is a block diagram for terminal accommodation of various speeds to which this invention is applied, and FIG. 4 is an F-bit terminal accommodation diagram. FIG. 5 is a block configuration diagram showing an example of detecting the data rate identification F bit pattern on multiple lines; FIG. 6 is a waveform diagram showing the detection clock; FIG. 7 is a diagram showing an example of the pattern.
Figure 8 is an explanatory diagram of 64Kb/s universal signal.
The figure is a diagram illustrating a terminal accommodation configuration in which the terminal speed can be switched when the present invention is applied. 1... terminal, 2... home line termination device, 3...
Subscriber line, 4... In-office line termination device, 5... Multiplexing device, 6... Multiplexing line, 7... In-office line termination device, 8... Switching office, 9... Inter-office line, 10, 1
1, 12, 13... terminal accommodation group, 14... F bit pattern generation circuit, 15... F bit pattern insertion circuit, 16... 64 Kb/s multiple line speed unit memory area, 17... shift register, 18...
...Pattern detection circuit, 19...Encoder, 20
...Selection circuit.

Claims (1)

[Claims] 1. In a method where a data terminal group has multiple speed types and the data of these data terminals is assembled into frames and time-division multiplexed, the pattern consisting of the F bit for synchronization within the frame is set to the speed determined by the storage location classification. Depending on the type, the F
A time division multiplexing system characterized in that a speed type is identified by detecting a bit pattern by a circuit that detects an F bit pattern used in a time division multiplexed frame and encodes the same.