JPS6347259B2 - - Google Patents
Info
- Publication number
- JPS6347259B2 JPS6347259B2 JP56191171A JP19117181A JPS6347259B2 JP S6347259 B2 JPS6347259 B2 JP S6347259B2 JP 56191171 A JP56191171 A JP 56191171A JP 19117181 A JP19117181 A JP 19117181A JP S6347259 B2 JPS6347259 B2 JP S6347259B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- stacked
- ceramic substrate
- circuit boards
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は機能素子を３次元的に積み重ねて、
単位面積当りの集積度を高密度化することができ
る半導体装置に関するものである。[Detailed description of the invention] This invention stacks functional elements three-dimensionally,
The present invention relates to a semiconductor device capable of increasing the degree of integration per unit area.
第１図は従来の半導体装置を示す断面図であ
る。同図において、１はセラミツク基板、２は該
セラミツク基板１上に形成されたメモリあるいは
論理回路等を形成したチツプ、３は内部リード、
４はチツプ２に形成したパツド６と内部リード３
とを接続する金線もしくはAl線等の接続リード、
５は前記内部リード３に接続する外部リード、７
は封止蓋である。 FIG. 1 is a sectional view showing a conventional semiconductor device. In the figure, 1 is a ceramic substrate, 2 is a chip with a memory or logic circuit formed on the ceramic substrate 1, 3 is an internal lead,
4 is a pad 6 formed on the chip 2 and an internal lead 3
Connection lead such as gold wire or Al wire to connect
5 is an external lead connected to the internal lead 3; 7
is a sealing lid.
このように、従来の半導体装置では１チツプを
１セラミツク容器あるいは１プラスチツクパツケ
ージ内に収納し、金線４―内部リード３―外部リ
ード５の経路で外部との電気的接続を与えてい
た。 As described above, in the conventional semiconductor device, one chip is housed in one ceramic container or one plastic package, and electrical connection with the outside is provided through the path of gold wire 4, internal lead 3, and external lead 5.
従来の半導体装置は以上のように構成されてい
るので、実装密度を上げる方法として、平面上
に、配列するものであるため、その高密度化に限
度がある欠点があつた。 Since conventional semiconductor devices are configured as described above, the method of increasing the packaging density is to arrange them on a plane, which has the disadvantage that there is a limit to how high the density can be increased.
この発明は上記のような欠点を除去するために
なされたもので、高密度化及び高速化の可能な半
導体装置を得ることを目的とする。 The present invention was made to eliminate the above-mentioned drawbacks, and aims to provide a semiconductor device that can achieve higher density and higher speed.
この発明に係る半導体装置は、その表面に突起
電極を有する第１及び第２の半導体集積回路基板
をその裏面同士を接触させて接合し、この基板接
合体を複数個積重ね、上記複数の半導体集積回路
基板の電極パツド間を配線接続したものである。 A semiconductor device according to the present invention includes first and second semiconductor integrated circuit substrates having protruding electrodes on their surfaces, which are joined by bringing their back surfaces into contact with each other, and a plurality of these substrate assemblies are stacked, and the plurality of semiconductor integrated circuit boards are stacked. This is a wiring connection between electrode pads on a circuit board.
この発明においては、上記構成とすることによ
り、装置を高密度化かつ高速化することができ
る。 In this invention, by having the above-mentioned structure, the device can be made denser and faster.
以下、この発明の一実施例を第２図において説
明する。同図において、１はセラミツク基板、３
は内部リード、４は金線又はAl線等の金属リー
ド、６は回路素子が形成されたチツプ状の半導体
集積回路基板９―１〜９―ｎの主表面上の周辺部
に位置して形成されたパツド、８は半導体集積回
路基板９―１〜９―ｎの主表面上に形成された突
起電極、９―１〜９―ｎは大きさが異なる例えば
メモリ回路を形成した半導体集積回路基板であ
り、同図に示されている如く、セラミツク基板１
上に半導体集積回路基板９―１をその突起電極を
上にして積重ね、さらに２つの半導体集積回路基
板を裏面同士を接触させて接合し、この基板接合
体を複数個上記半導体集積回路基板９―１上に積
重ねている。また最上段の基板接合体上には半導
体集積回路基板９―ｎをその突起電極を下にして
積重ねている。ここでは半導体集積回路基板は上
層のものほど小さく、また各基板接合体の上側の
基板はその周辺部のパツド間を金線４で接続して
いる。 An embodiment of the present invention will be described below with reference to FIG. In the figure, 1 is a ceramic substrate, 3
4 is an internal lead, 4 is a metal lead such as a gold wire or Al wire, and 6 is formed at a peripheral portion on the main surface of a chip-shaped semiconductor integrated circuit board 9-1 to 9-n on which a circuit element is formed. The pads 8 are protruding electrodes formed on the main surfaces of semiconductor integrated circuit boards 9-1 to 9-n, and 9-1 to 9-n are semiconductor integrated circuit boards having different sizes, for example, on which memory circuits are formed. As shown in the figure, the ceramic substrate 1
A semiconductor integrated circuit board 9-1 is stacked on top of the semiconductor integrated circuit board 9-1 with its protruding electrode facing upward, and two semiconductor integrated circuit boards are then bonded with their back surfaces in contact with each other, and a plurality of these board assemblies are assembled into the semiconductor integrated circuit board 9-1. It is stacked on top of 1. Furthermore, semiconductor integrated circuit boards 9-n are stacked on the uppermost substrate assembly with their protruding electrodes facing down. Here, the semiconductor integrated circuit boards are smaller as they are in the upper layer, and the pads on the upper side of each board assembly are connected by gold wires 4 between the pads in the periphery.
以上、説明したように、バンプ８間―パツド６
―金線４、又はバンプ８間―金線４―パツド６等
の組み合せによる電気経路により、半導体集積回
路基板９―１〜９―ｎ上の集積回路は外部と内部
リード３―金線４を通して電気的接触をすること
ができる。 As explained above, between bump 8 and pad 6
The integrated circuits on the semiconductor integrated circuit boards 9-1 to 9-n are connected to the outside through the internal leads 3 and 4 through the electrical path formed by the combination of the gold wire 4 or between the bumps 8, the gold wire 4, and the pad 6. Electrical contact can be made.
なお、上記実施例ではセラミツク基板１と半導
体集積回路基板９―１の裏面と接触させて接合し
この上に基板接合体を積重ねているが、セラミツ
ク基板１上にバンプを形成し、この上に上記基板
接合体を直接積重ねてもよい。 In the above embodiment, the ceramic substrate 1 and the back surface of the semiconductor integrated circuit board 9-1 are brought into contact and bonded, and the substrate assembly is stacked thereon. However, bumps are formed on the ceramic substrate 1, and the The above substrate assemblies may be directly stacked.
また、第３図のように多層セラミツク基板１０
上に基板接合体を、その半導体集積回路基板１１
―１〜１１―ｎが小さいものから順次三次元的に
積み重ねてもよい。但し第３図には示されていな
いが、多層セラミツク基板１０上の各バンプ８は
バンプ間もしくは内部リードと所望の電気的接続
がなされ、その内部リードを介して外部リードと
所望の接続ができるものである。 Moreover, as shown in FIG. 3, a multilayer ceramic substrate 10
A substrate assembly is placed on top of the semiconductor integrated circuit board 11.
-1 to 11-n may be stacked three-dimensionally in order from the smallest one. However, although not shown in FIG. 3, each bump 8 on the multilayer ceramic substrate 10 has a desired electrical connection between the bumps or with an internal lead, and a desired connection can be made with an external lead via the internal lead. It is something.
このような本実施例では、
(A) 半導体集積回路基板を複数層積層したので、
装置の高密度化及び高速化が可能となる。 In this example, (A) multiple layers of semiconductor integrated circuit boards are stacked;
It becomes possible to increase the density and speed of the device.
(B) 配線長が短くなるので、浮遊容量が低下し、
より高速化が可能になる。(B) As the wiring length becomes shorter, stray capacitance decreases,
Faster speeds are possible.
(C) 半導体基板の裏面同士を接合したので、装置
全体の熱容量を大きくしてさらに一層の高速化
を行うことができる。(C) Since the back surfaces of the semiconductor substrates are bonded to each other, the heat capacity of the entire device can be increased and the speed can be further increased.
(D) 各層の半導体集積回路基板のテストをウエハ
段階で行うことができるため、良品チツプのみ
を積層することができ高い良品率を確保するこ
とができる。(D) Since each layer of the semiconductor integrated circuit board can be tested at the wafer stage, only non-defective chips can be stacked, and a high rate of non-defective products can be ensured.
(E) 基板接合体間の接続をフリツプチツプボンデ
イングで行うので配線接続の信頼性を高めるこ
とができる。(E) Since the connections between the substrate assemblies are made by flip-chip bonding, the reliability of wiring connections can be improved.
以上のようにこの発明に係る半導体装置によれ
ば、その表面に突起電極を有する２つの半導体集
積回路基板をその裏面同士を接触させて接合し、
この基板接合体をセラミツク基板上に複数個積重
ねるようにしたので、装置の高密度化及び高速化
を行うことができる効果がある。 As described above, according to the semiconductor device of the present invention, two semiconductor integrated circuit boards having protruding electrodes on their surfaces are joined by bringing their back surfaces into contact with each other,
Since a plurality of these substrate assemblies are stacked on the ceramic substrate, it is possible to increase the density and speed of the device.
第１図は従来の半導体装置を示す断面図、第２
図は本発明の一実施例による半導体装置を示す断
面、第３図はこの発明の他の実施例を示す断面図
である。
１…セラミツク基板、２…チツプ、３…内部リ
ード、４…金線、５…外部リード、６…パツド、
７…封止蓋、８…突起電極、９―１〜９―ｎ，１
１―１〜１１―ｎ…半導体集積回路基板、１０…
多層セラミツク基板。
Figure 1 is a sectional view showing a conventional semiconductor device, Figure 2 is a cross-sectional view showing a conventional semiconductor device;
The figure is a sectional view showing a semiconductor device according to one embodiment of the invention, and FIG. 3 is a sectional view showing another embodiment of the invention. 1... Ceramic substrate, 2... Chip, 3... Internal lead, 4... Gold wire, 5... External lead, 6... Pad,
7... Sealing lid, 8... Projection electrode, 9-1 to 9-n, 1
1-1 to 11-n...Semiconductor integrated circuit board, 10...
Multilayer ceramic substrate.
Claims (1)
半導体集積回路基板をその裏面同士を接触させて
接合し、 この基板接合体をセラミツク基板上に複数個積
層し、上記複数の半導体集積回路基板の電極パツ
ド間を配線接続してなることを特徴とする半導体
装置。[Claims] 1. First and second semiconductor integrated circuit substrates having protruding electrodes on their surfaces are joined by bringing their back surfaces into contact with each other, and a plurality of these substrate assemblies are stacked on a ceramic substrate, and the above-mentioned A semiconductor device characterized in that it is formed by connecting electrode pads of a plurality of semiconductor integrated circuit boards with wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56191171A JPS5892230A (en) | 1981-11-27 | 1981-11-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56191171A JPS5892230A (en) | 1981-11-27 | 1981-11-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5892230A JPS5892230A (en) | 1983-06-01 |
| JPS6347259B2 true JPS6347259B2 (en) | 1988-09-21 |
Family
ID=16270076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56191171A Granted JPS5892230A (en) | 1981-11-27 | 1981-11-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5892230A (en) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6262451U (en) * | 1985-10-04 | 1987-04-17 | ||
| US5614766A (en) * | 1991-09-30 | 1997-03-25 | Rohm Co., Ltd. | Semiconductor device with stacked alternate-facing chips |
| US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
| JPH06244231A (en) * | 1993-02-01 | 1994-09-02 | Motorola Inc | Airtight semiconductor device and manufacturing method thereof |
| EP0631144A1 (en) * | 1993-06-24 | 1994-12-28 | Koninklijke Philips Electronics N.V. | High voltage differential sensor having a capacitive attenuator |
| US5385632A (en) * | 1993-06-25 | 1995-01-31 | At&T Laboratories | Method for manufacturing integrated semiconductor devices |
| US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
| US5715144A (en) * | 1994-12-30 | 1998-02-03 | International Business Machines Corporation | Multi-layer, multi-chip pyramid and circuit board structure |
| US6014586A (en) * | 1995-11-20 | 2000-01-11 | Pacesetter, Inc. | Vertically integrated semiconductor package for an implantable medical device |
| KR100443484B1 (en) * | 1996-02-19 | 2004-09-18 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device and method for fabricating the same |
| US5907903A (en) * | 1996-05-24 | 1999-06-01 | International Business Machines Corporation | Multi-layer-multi-chip pyramid and circuit board structure and method of forming same |
| JP3825181B2 (en) | 1998-08-20 | 2006-09-20 | 沖電気工業株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP2002033441A (en) * | 2000-07-14 | 2002-01-31 | Mitsubishi Electric Corp | Semiconductor device |
| JP2002270759A (en) | 2001-03-14 | 2002-09-20 | Matsushita Electric Ind Co Ltd | Semiconductor chip and multi-chip module |
| JP2002373969A (en) * | 2001-06-15 | 2002-12-26 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing semiconductor device |
| JP3794942B2 (en) | 2001-07-09 | 2006-07-12 | 松下電器産業株式会社 | Multichip module and connection test method thereof |
| JP2003185710A (en) | 2001-10-03 | 2003-07-03 | Matsushita Electric Ind Co Ltd | Multi-chip module, semiconductor chip, and inter-chip connection test method of multi-chip module |
| EP1472730A4 (en) * | 2002-01-16 | 2010-04-14 | Mann Alfred E Found Scient Res | HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE |
| US7211884B1 (en) | 2002-01-28 | 2007-05-01 | Pacesetter, Inc. | Implantable medical device construction using a flexible substrate |
| US8089142B2 (en) | 2002-02-13 | 2012-01-03 | Micron Technology, Inc. | Methods and apparatus for a stacked-die interposer |
| US6590282B1 (en) * | 2002-04-12 | 2003-07-08 | Industrial Technology Research Institute | Stacked semiconductor package formed on a substrate and method for fabrication |
| WO2004038798A2 (en) * | 2002-10-22 | 2004-05-06 | Unitive International Limited | Stacked electronic structures including offset substrates |
| JP2009302212A (en) | 2008-06-11 | 2009-12-24 | Fujitsu Microelectronics Ltd | Semiconductor device and method of manufacturing the same |
| KR101774938B1 (en) | 2011-08-31 | 2017-09-06 | 삼성전자 주식회사 | Semiconductor package having supporting plate and method of forming the same |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5081475A (en) * | 1973-11-19 | 1975-07-02 | ||
| JPS5845822B2 (en) * | 1975-03-07 | 1983-10-12 | セイコーエプソン株式会社 | Shuyuuseki Cairo |
| JPS5337383A (en) * | 1976-09-20 | 1978-04-06 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS56103455A (en) * | 1980-01-22 | 1981-08-18 | Fujitsu Ltd | Semiconductor ic device |
| JPS56137665A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
| JPS56148857A (en) * | 1980-04-18 | 1981-11-18 | Mitsubishi Electric Corp | Semiconductor device |
-
1981
- 1981-11-27 JP JP56191171A patent/JPS5892230A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5892230A (en) | 1983-06-01 |
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