JPS6347271B2 - - Google Patents
Info
- Publication number
- JPS6347271B2 JPS6347271B2 JP57043261A JP4326182A JPS6347271B2 JP S6347271 B2 JPS6347271 B2 JP S6347271B2 JP 57043261 A JP57043261 A JP 57043261A JP 4326182 A JP4326182 A JP 4326182A JP S6347271 B2 JPS6347271 B2 JP S6347271B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- cap
- external lead
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of flexible or folded printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は多層混成集積回路装置の改良に関する
多層混成集積回路として周知のものにマイクロモ
ジユールがある。マイクロモジユールは複数の絶
縁基板に所望の小型回路素子を組み込みスルーホ
ール電極を介して積層したものである。斯るマイ
クロモジユールでは小型化は図れるが、組み込み
できる回路素子の制約が大きく、すべての回路に
適用できるものではない。またスルーホール電極
を不可欠としているので製造技術上も量産性に乏
しい。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvement of a multilayer hybrid integrated circuit device. A well-known multilayer hybrid integrated circuit is a micromodule. A micromodule is a structure in which desired small circuit elements are built into a plurality of insulating substrates and laminated via through-hole electrodes. Although such micromodules can be miniaturized, there are significant restrictions on the circuit elements that can be incorporated, and they cannot be applied to all circuits. Furthermore, since through-hole electrodes are essential, mass productivity is poor in terms of manufacturing technology.
そこで多層の簡易化された構造を第1図に示
す。1は混成集積回路基板、2は枠状の離間材、
3は外部リードである。この構造では別々の混成
集積回路基板1に別個の工程で所望の回路素子を
付着し、外部リード3を電極パツド(図示せず)
に固着した後、枠状の離間材2で両基板1,1を
一体化するものである。従つてパツケージ上では
多層構造と言えるが、回路上は別個の回路を近接
したにすぎない。また両基板1,1は別工程で製
造されるので量産性も今一歩の感が多い。 Therefore, a simplified multilayer structure is shown in FIG. 1 is a hybrid integrated circuit board, 2 is a frame-shaped spacer,
3 is an external lead. In this structure, desired circuit elements are attached to separate hybrid integrated circuit boards 1 in separate steps, and external leads 3 are connected to electrode pads (not shown).
After the two substrates 1, 1 are fixed to each other, the two substrates 1, 1 are integrated with a frame-shaped spacer 2. Therefore, although it can be said to have a multilayer structure on the package, on the circuit it is simply a combination of separate circuits placed close to each other. Furthermore, since the two substrates 1, 1 are manufactured in separate processes, mass production is likely to be a step ahead.
本発明は斯点に鑑みてなされ、従来の欠点を大
巾に改善した多層混成集積回路装置を提供するも
のである。以下に第2図および第3図を参照して
本発明の一実施例を詳述する。 The present invention has been made in view of the above, and an object thereof is to provide a multilayer hybrid integrated circuit device that greatly improves the conventional drawbacks. An embodiment of the present invention will be described in detail below with reference to FIGS. 2 and 3.
本発明に依る多層混成集積回路はU字状に曲折
した金属基板10と、該基板10の内側主面に付
着された回路素子11と、基板10の少くとも両
端に設けた電極パツド12と、該電極パツド12
に固着された外部リード13より構成される。 The multilayer hybrid integrated circuit according to the present invention includes a metal substrate 10 bent into a U-shape, a circuit element 11 attached to the inner main surface of the substrate 10, and electrode pads 12 provided at at least both ends of the substrate 10. The electrode pad 12
The external lead 13 is fixed to the external lead 13.
金属基板10としては表面を陽極酸化したアル
ミニウムを用い、放熱性を向上させると同時に曲
折加工を容易にならしめる。 The metal substrate 10 is made of aluminum whose surface is anodized to improve heat dissipation and at the same time facilitate bending.
斯る基板10は第2図に示す如く、平板状の状
態で所望の回路を形成することにより従来の製造
技術をそのまま利用できる。基板10上には銅箔
による導電路14、スクリーン印刷による抵抗体
15あるいはトランジスター、IC16等を付着
して所望の回路を形成する。なお曲折される基板
10の中央部には全く回路を形成せず、曲折を容
易にするためにスリツト17を形成する。 As shown in FIG. 2, such a substrate 10 can be manufactured using conventional manufacturing techniques by forming a desired circuit in a flat plate state. A desired circuit is formed on the substrate 10 by attaching a conductive path 14 made of copper foil, a resistor 15 by screen printing, a transistor, an IC 16, etc. Note that no circuit is formed in the center of the substrate 10 to be bent, but a slit 17 is formed to facilitate bending.
電極パツド12は前述した導電路14を延在さ
せて基板10の両端に一定間隔で設ける。斯る電
極パツド12は対向するものと位置的に対応させ
ておく。 The electrode pads 12 extend the aforementioned conductive paths 14 and are provided at regular intervals on both ends of the substrate 10. Such electrode pads 12 are made to correspond in position to the opposing pads.
斯上した基板10は中央部でU字状に曲折し
て、基板10の回路素子11を設けた内側主面を
一定間隔で対向させる。 The substrate 10 thus prepared is bent into a U-shape at the center, so that the inner main surfaces of the substrate 10 on which the circuit elements 11 are provided face each other at a constant interval.
外部リード13は各電極パツド12に半田によ
り固着されている。この外部リード13の先端部
を第3図の如くかぶら状になし、このかぶら状先
端部18を対向する電極パツド12に半田付けし
ても良い。 External leads 13 are fixed to each electrode pad 12 by solder. The tip of the external lead 13 may be formed into a cap shape as shown in FIG. 3, and the cap-shaped tip 18 may be soldered to the opposing electrode pad 12.
斯る本発明の多層混成集積回路装置では、金属
基板10を用いることにより同一工程で製造した
基板を最後にU字状に曲折するので、まず従来の
枠状の離間材を不要とし、且つ生産性の向上を図
れる利点を有する。 In the multilayer hybrid integrated circuit device of the present invention, by using the metal substrate 10, the substrates manufactured in the same process are finally bent into a U-shape, thereby eliminating the need for the conventional frame-shaped spacer and reducing the production time. It has the advantage of improving sexual performance.
次に基板10の曲折部には導電路14を配置で
きないので両面の回路の接続を行えない欠点を有
しているが、この欠点をかぶら状先端部18を有
する外部リード13によつて解消できる。すなわ
ち、かぶら状先端部18により電極の取り出しと
同時に両電極を電気的に接続できる両機能を実現
できる。従つて外部リード13として不要のもの
は切断除去しかぶら状先端部18による上下接続
ができる。 Next, since the conductive path 14 cannot be arranged at the bent portion of the board 10, circuits on both sides cannot be connected. However, this drawback can be overcome by the external lead 13 having the capped tip 18. . That is, the turnip-shaped tip 18 can realize both functions of taking out the electrode and electrically connecting both electrodes at the same time. Therefore, unnecessary parts of the external leads 13 can be cut and removed, and vertical connections can be made using the beveled tips 18.
以上に詳述した如く本発明に依ればU字状金属
基板10とかぶら状外部リード13により、極め
て容易に且つ量産性に富む多層混成集積回路装置
を実現できる。 As described in detail above, according to the present invention, a multilayer hybrid integrated circuit device that is extremely easy to mass-produce can be realized by using the U-shaped metal substrate 10 and the dovetail-shaped external leads 13.
第1図は従来例を説明する断面図、第2図およ
び第3図は本発明を説明する平面図および断面図
である。
主な図番の説明、10は金属基板、11は回路
素子、12は電極パツド、13はかぶら状外部リ
ード、17はスリツトである。
FIG. 1 is a sectional view illustrating a conventional example, and FIGS. 2 and 3 are a plan view and a sectional view illustrating the present invention. Explanation of the main figure numbers: 10 is a metal substrate, 11 is a circuit element, 12 is an electrode pad, 13 is a head-shaped external lead, and 17 is a slit.
Claims (1)
れた金属基板と該基板の内側主表面に絶縁薄層を
介して形成した所望の回路素子と前記基板の両端
に対応する様に設けた電極パツドと該電極パツド
に固着されたかぶら状の先端部を有する外部リー
ドと該外部リードの不要部分を切断除去して形成
されたかぶら状の接続体とを備え、該かぶら状の
接続体で上下回路を接続することを特徴とする多
層混成集積回路装置。1. A metal substrate bent into a U-shape with a slit in the center, a desired circuit element formed on the inner main surface of the substrate via a thin insulating layer, and electrodes provided corresponding to both ends of the substrate. A pad, an external lead having a cap-shaped tip fixed to the electrode pad, and a cap-shaped connecting body formed by cutting and removing an unnecessary part of the external lead, and the cap-shaped connecting body A multilayer hybrid integrated circuit device characterized by connecting circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043261A JPS58159362A (en) | 1982-03-17 | 1982-03-17 | Multi-layer hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043261A JPS58159362A (en) | 1982-03-17 | 1982-03-17 | Multi-layer hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58159362A JPS58159362A (en) | 1983-09-21 |
| JPS6347271B2 true JPS6347271B2 (en) | 1988-09-21 |
Family
ID=12658903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57043261A Granted JPS58159362A (en) | 1982-03-17 | 1982-03-17 | Multi-layer hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159362A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4891827B2 (en) * | 2007-03-30 | 2012-03-07 | 株式会社アルファ | Handle device |
-
1982
- 1982-03-17 JP JP57043261A patent/JPS58159362A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58159362A (en) | 1983-09-21 |
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