JPS6347288B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a DA (digital-to-analog) converter for converting a digital signal to an analog signal, and is particularly aimed at improving the characteristics of a multi-bit DA converter. .

Recently, PCM (Pulse Code Modulation)
Development of digital audio equipment using technology is active. PCM recording uses a magnetic tape as a medium, converts an acoustic signal (analog signal) into a digital signal and then records it on the magnetic tape, and converts the digital signal picked up from the magnetic tape into an analog signal and plays it back. playback machine,
2. Description of the Related Art A digital audio disc playback device has been proposed as a high-quality audio device, which picks up a digital signal from a disk on which the digital signal has been recorded, converts it into an analog signal, and plays it back. Therefore, audio devices that use these digital signals require a DA converter to convert the digital signals into analog signals.

As a DA converter, one that utilizes a ladder resistance network as shown in FIG. 1 is conventionally known. Figure 1 shows a DA converter using a 4-bit resistor ladder network, consisting of resistors 1, 2, and 3 with a resistance value R, and resistors 4, 2, and 3 with a resistance value 2R.
5, 6, 7, 8, and 9, switches 10, 11, 12, and 13 corresponding to each bit, and a power supply 14. This is done so that the output voltage is determined. A DA converter that uses such a ladder resistance network can generate a stepped output voltage with constant steps depending on the number of bits, but as the number of bits increases, As shown in the figure, there are stages that are not smoothly continuous in the center of the output. This is due to errors in the resistors that make up the ladder resistor network, and the reason why the step error is greatest at the center of the output is that the maximum bit (MSB), which has a weight of half of the total amplitude, This is because the absolute value of the error becomes maximum when the value changes to "1" or from "1" to "0".
The step error at the center of the output has a significant adverse effect, particularly on DA converters used in devices that require a large number of bits and high resolution, such as digital audio disc playback devices. In other words, in such a device, the center of the output is the zero level, and the output must be generated based on the positive and negative digital signals around the zero level, but the error caused by the step error at the zero level must be generated. If continuity occurs, large distortions and noise will occur when playing back low level signals. This is extremely inconvenient, especially for the auditory sense, and there is a great need for improvement. Figure 3 shows the relationship between the signal magnitude and the amount of discontinuity. Range A shows the small level signal range that is an important factor for sound quality, and range B shows the entire amplitude range of the output signal. .

Precise trimming of the resistors that make up the ladder resistor network minimizes errors in each resistor and helps eliminate discontinuities in the center of the output. However, trimming the resistor requires a special process and has the drawback of increasing the cost of the DA converter. Furthermore, monotonicity can be easily obtained by trimming the resistors only for DA converters of about 10 bits at most, and for multi-bits as large as 16 bits such as digital audio disk playback devices.
In a DA converter, it is extremely difficult to obtain monotonicity through adjustment by trimming the resistor.

The present invention has been made in view of the above points, and will be described below based on one embodiment of the present invention with reference to the drawings. Figure 4 shows a 4-bit DA converter, in which 15 to 18 are the first to fourth signal input terminals to which digital signals are applied, and 19 to 21 are the first to fourth signal input terminals.
22 to 3 are first to third NAND circuits, 25 to 28 are first to fourth resistors having a resistance value R, 29 to 36 are fifth to twelfth resistors having a resistance value 2R, and 37 is a signal output terminal from which an analog signal can be obtained. Thus, the fourth input terminal 18 to which the most significant bit (MSB) signal is applied is
It is connected to one input terminal of the AND circuits 29 to 31 and the NAND circuits 22 to 24, and the first to third input terminals 15 to 17 are connected to the other input terminal of the AND circuits 29 to 31 and the NAND circuits 22 to 24. are connected to their corresponding terminals. Further, the first and second resistors 25 and 26, the fifth to seventh resistors 29 to 31, the eleventh resistor 35, the third and fourth resistors 27 and 28, the eighth to tenth resistors 32 to 34 and the twelfth resistor 36 each constitute a ladder resistance network, and the output terminal 37 is provided at a connection point between the ladder resistance networks.

When the DA converter shown in FIG. 4 is used in the offset binary system with two advances, the input/output relationship will be as shown in FIG. 5, which will be explained in detail. When the MSB signal applied to the fourth input terminal 18 is a negative signal of "0", the outputs of the first to third AND circuits 29 to 31 are forced to "L", and the outputs of the first to third NAND circuits 29 to 31 are forced to "L". The outputs of the circuits 22 to 24 become "H" or "L" depending on the digital signals applied to the first to third input terminals 15 to 17, so the output terminal 37 has a signal as shown in FIG. An output signal is generated. Then, at the point where the digital signals applied to the first to fourth input terminals 15 to 18 change from "0111" to "1000", the fourth
Since the MSB signal applied to the input terminal 18 becomes "1", the first to third NAND circuits 22 to 24
The output of is forcibly set to "H" and an "H" signal is applied to one end of the eleventh resistor 35. Therefore, an output of "+8" is generated at the output terminal 37 as a reference. After that, the first to third input terminals 1
Depending on the digital signals applied to 5 to 17,
The output signals of the first to third AND circuits 19 to 21 become "1" or "0", and an output signal as shown in FIG. 5 is generated at the output terminal 37. FIG. 6 shows the output signal of the DA converter shown in FIG. 4. From FIG. , “−
It can be seen that the values are increased by one step at equal intervals from "+0" which is one step higher than "0". By the way, it can be seen from Figure 6 that there is one step between "-0" and "+0", but "-
When output signals of “0” and “+0” are generated,
This is when the digital signals applied to the first to fourth input terminals 15 to 18 are "0111" and "1000", respectively. When the digital signal is "0111", the MSB signal is "0", so the outputs of the first to third AND circuits 19 to 21 are forced to "L", and one end of the eleventh resistor 35 is "L". Since the "L" signal is applied and all bit signals other than MSB are "1", the first to third NAND circuits 22 to 2
The output of 4 becomes "H". On the other hand, when the digital signal is "1000", the MSB signal is "1", so the outputs of the first to third NAND circuits 22 to 24 are forced to "H", and the eleventh resistor 35 An "H" signal is applied to one end of the
Since all bit signals other than MSB are "0", the outputs of the first to third AND circuits 19 to 21 become "L". That is, even if the digital signals applied to the first to fourth input terminals 15 to 18 change from "0111" to "1000", the first to third AND circuits 19 to 21 and the first to third NAND circuits Since the outputs of the terminals 22 to 24 do not change and only the signal applied to one end of the eleventh resistor 35 changes from "L" to "H", the output terminal 37
The output signal generated in this process has no discontinuous parts and changes smoothly and continuously.

Further, as shown in FIG. 4, there is a first gate circuit section consisting of NAND circuits 22 to 24 to which a quantized digital signal is applied using the MSB signal as a switching signal, or a second gate circuit section consisting of AND circuits 19 to 21. Forcibly determines the output from the gate circuit section,
Since the ladder resistance network used is switched,
It is possible to process a 4-bit input signal with two circuit configurations for 3 bits, and the gate circuits such as AND circuits and NAND circuits that constitute the first and second gate circuit sections can be processed in response to conventional bit signals. The gate circuit functions as a switch and a power source, and since an existing integrated circuit can be used as the gate circuit, the circuit configuration is simple.

As described above, the present invention is excellent in that it can provide a DA converter with good characteristics, and is particularly useful for high-fidelity audio.

In addition, in the examples, in order to simplify the explanation,
Although a 4-bit DA converter has been described, the number of bits is not limited, and the present invention is naturally applicable to multi-bit DA converters such as 8 bits and 16 bits.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional DA converter, Fig. 2 is a characteristic diagram showing its output waveform, and Fig. 3 is a circuit diagram showing a conventional DA converter.
4 is a circuit diagram showing an embodiment of the present invention, FIG. 5 is a chart showing the input/output relationship, and FIG. 6 is a characteristic diagram showing the amount of discontinuity in the circuit shown in FIG. FIG. 3 is a characteristic diagram showing an output waveform. Explanation of main drawing numbers 15, 16, 17, 18...
Input terminal, 19, 20, 21...AND circuit, 2
2, 23, 24... NAND circuit, 37... Output terminal.

Claims (1)

[Claims] 1 Consisting of gate circuits whose number is one less than the number of bits of the input digital signal, and the most significant bit signal of the digital signal is applied to one input terminal of each of the gate circuits, and the most significant bit signal of the digital signal is applied to the other input terminal of the gate circuit. Each bit signal other than the most significant bit in the digital signal is applied to the input terminal of each of the first bits connected in parallel with each other.
and a second gate circuit section, first and second ladder resistance circuit networks to which outputs from the gate circuits constituting the first and second gate circuit sections are respectively applied and connected in parallel to each other; The most significant bit signal of the digital signal is applied to the output terminal provided at the connection point between the first and second ladder resistance circuit networks and the second ladder resistance network, and the signal level obtained at the output terminal is set to a level. means for shifting, when the most significant bit signal in the digital signal is "0", the output of the gate circuit constituting the second gate circuit section is forcibly set to "L", and the output of the gate circuit constituting the second gate circuit section is forced to be "L" Each of the gate circuits constituting the section generates a signal corresponding to the bit signal in the digital signal input to the other input terminal, and when the most significant bit signal in the digital signal is "1", the gate circuit generates a signal corresponding to the bit signal in the digital signal input to the other input terminal. The output of the gate circuit constituting the first gate circuit section is forcibly set to "H", and the bit signal in the digital signal inputted to the other input terminal from the gate circuit constituting the second gate circuit section. and applying the most significant bit signal of the digital signal to the second ladder resistor network, so that when the most significant bit signal is switched, the first bit signal is switched.
and a DA converter characterized in that the signal level obtained at the output terminal is changed without changing the output from the gate circuit constituting the second gate circuit section.