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JPS6347306B2 - - Google Patents
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JPS6347306B2 - - Google Patents

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Publication number
JPS6347306B2
JPS6347306B2 JP56213626A JP21362681A JPS6347306B2 JP S6347306 B2 JPS6347306 B2 JP S6347306B2 JP 56213626 A JP56213626 A JP 56213626A JP 21362681 A JP21362681 A JP 21362681A JP S6347306 B2 JPS6347306 B2 JP S6347306B2
Authority
JP
Japan
Prior art keywords
circuit
signal
training
data
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56213626A
Other languages
Japanese (ja)
Other versions
JPS58116848A (en
Inventor
Takashi Kako
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56213626A priority Critical patent/JPS58116848A/en
Publication of JPS58116848A publication Critical patent/JPS58116848A/en
Publication of JPS6347306B2 publication Critical patent/JPS6347306B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

(a) 発明の技術分野 本発明は伝送路の特性を補償する機能を有する
データモデムのトレーニング時において、受信キ
ヤリアの瞬断発生時、その瞬断耐力特性の向上を
図つたトレーニング検出方式に関するものであ
る。 (b) 技術の背景 データ通信の受信側において、受信キヤリアの
瞬断が起つた場合、瞬断が復旧した以降のデータ
を無効とせずに継続して有効なデータを受信でき
る瞬断耐力向上が要望されている。 (c) 従来技術と問題点 電話回線を利用したデータ伝送では、AGC回
路、キヤリア再生回路、タイミング発生回路、自
動等化器などの受信側の諸回路への信号の引込み
のために、データ信号の送信開始に先立つて特定
のトレーニング信号を送信する。このトレーニン
グ信号の形式には下記の表に示すものがある
(CCITT資料COM.SP.A−No.148による)。ここで
「S」はセグメント、「全」は全トレーニング信号
を意味する。
(a) Technical Field of the Invention The present invention relates to a training detection method for improving the instantaneous interruption tolerance characteristics when a receiving carrier interruption occurs during training of a data modem that has a function of compensating for the characteristics of a transmission path. It is. (b) Background of the technology On the receiving side of data communication, when a momentary interruption of the receiving carrier occurs, it is possible to improve momentary interruption tolerance so that valid data can continue to be received without invalidating the data after the momentary interruption has been recovered. It is requested. (c) Prior art and problems In data transmission using a telephone line, the data signal is A specific training signal is transmitted prior to the start of transmission. The format of this training signal is shown in the table below (according to CCITT document COM.SP.A-No. 148). Here, "S" means a segment, and "total" means the entire training signal.

【表】 トレーニング信号のセグメント1には信号は含
まれていないが、セグメント2との変換点がデー
タ受信開始の検出に用いられる。トレーニング信
号のセグメント2は二つの信号要素の繰返しから
なる。第1図に示すように、その第1の信号要素
Aは相対振幅3を持ちそして180゜の絶対位相基準
を定める。第2の信号要素Bはデータ速度で変
り、7200bit/secの時は(1−j)、9600bit/sec
の時は3(1−j)の各ベクトルである。セグメ
ント2は128シンボルインタバルの間ABAB……
…を繰返す。トレーニング信号のセグメント3
は、PN符号とも呼ばれるイコーライザコンデイ
シヨニングパターンに従つて変る二つの信号要素
からなる。その第1の信号要素Cは相対振幅3お
よび絶対位相0゜を持ち、第2の信号要素Dはデー
タ速度で変り、7200bit/secの時は(−1+j)、
9600bit/secの時は3(−1+j)の各ベクトル
である。イコーライザコンデイシヨニングパター
ンは擬似ランダムシーケンスであり、このシーケ
ンスが0のときCが、1のときDが発生する。ま
たセグメント4の信号はデスクランプラ回路の引
込みに用いられる。 このセグメント2の信号には復調キヤリアが含
まれている。即ちベクトルAおよびBはベクトル
A′とCARの和およびベクトルB′とCARの和と考
えることができ、セグメント2がA、B、A、B
を繰り返すとき不変成分はCAR、交番成分は
A′とB′であり、交番成分A′、B′の和は零、不変
成分のCARがキヤリア信号である。 セグメント3について同様に不変成分従つてキ
ヤリア成分を求めてみると、ベクトルCおよびD
はベクトルA′とCAR′およびベクトルB′と
CAR′の和であるから、キヤリア成分はCAR′と
なり、これはセグメント2のキヤリア成分CAR
と位相が180゜ずれている。 イコライザ(自動等化器)の引込みに当つて
は、送信側で上記セグメント3の信号を送出する
と共に受信側でも同じ信号を発生し、例えば両者
を比較して波形補正に必要な信号を求める。この
ような操作を行うにはセグメント3の開始時点を
検知し、受信側で上記信号の発生を開始せねばな
らない。 従来、伝送路の影響等で障害が発生し、受信キ
ヤリアの瞬断が起つた場合瞬断耐力向上の方法と
して以下の2つが考えられる。 即ち、(イ)トレーニング検出を行わない方法、及
び(ロ)トレーニング検出を行う方法が実施されてい
た。(イ)トレーニング検出を行わない方法とはキヤ
ラクタ検出器のOFF時間を延ばして対処する方
式である。この従来方法は短い瞬断に対しては瞬
断耐力が理想的となるが、NET領域の時間に制
約が生じるため、長い時間の瞬断に対しては無効
となる。 さらに、(ロ)トレーニング検出を行う方法を実施
すると、長い瞬断に対して有効となるが、短い瞬
断に対してはオフセツトが生じる。 第2図は従来の(イ)方式(ロ)方式の瞬断時間とエラ
ー発生時間との特性関係図である。 (d) 発明の目的 本発明の目的は上記欠点を除去するもので、瞬
断によつて無効となるデータを最小限に抑え、瞬
断耐力特性向上を図つたデータモデム用トレーニ
ング検出方式を提供することを目的とするもので
ある。 (e) 発明の構成 受信信号を波形成形フイルタ経由で1信号要素
分遅延する第1の遅延回路と前記第1の遅延回路
を経由しない入力信号とを加算する加算回路と、
前記加算回路の出力を180゜遅延する第2の遅延回
路と、前記第2の遅延回路の出力を乗算回路に入
力し、一方前記第2の加算回路の出力を前記第2
の遅延回路を経由せずに前記乗算回路に入力し、
前記乗算回路の出力効果をタツプ付遅延素子経由
で符号判定に入力し、トレーニング信号かデータ
かを検出することを特徴とするデータモデム用ト
レーニング検出方式を提供することによつて達成
される。 (f) 発明の実施例 以下本発明の実施例を図面によつて詳述する。 第3図は本発明にて用いられるトレーニング信
号のシーケンス図である。トレーニング信号各セ
ブメントSEG1〜SEG4の内容は第1図にて説
明した通りの内容である。 第4図は本発明を適用したデータモデム用トレ
ーニング検出方式の一実施例を示した回路構成図
である。 図面において、ROFは入力信号の波形を成形
する波形成形フイルタ、Tは遅延素子、+は加算
回路、×は乗算回路、CJUはタツプ付遅延線から
の出力によりトレーニングかデータかを判定する
符号判定回路をそれぞれ示す。 通信線路を介して入力された信号はまず波形成
形フイルタROFに入力され、雑音成分等は除去
され、希望する受信信号のみを受信する。第3図
で示したセブメントSEG2にて信号要素AとB
とが入力されると、波形成形フイルタROFを経
由して遅延素子TAにて1信号要素分遅延させ加
算回路+にてA+Bの信号を取り出す。a点のA
+Bベクトル成分は図に示すようにマイナス虚数
成分のみとなる。次にA+Bの信号は遅延素子
TBにて180゜遅延させて、複素共役化すると、b点
のA+Bベクトル成分は図に示すようにプラス虚
数成分のみとなる。 該プラス虚数成分に変換したA+Bのベクトル
成分と、変換前のマイナス虚数のA+Bのベクト
ル成分とを乗算器×で乗算するとA+Bのベクト
ル成分は虚数から実数に変化され、その出力はト
レーニング信号の場合は実軸成分を極性で表わす
と+++++++++の結果が得られる。この出
力結果はタツプ付遅延素子TC〜TGの各タツプか
ら符号判定回路CTUに入力される。符号判定回
路CJUではタツプ付遅延素子からの出力結果の実
軸成分を極性で表わすと+++++++++の場
合は受信信号がトレーニングと判断し、タツプ付
遅延素子からの出力結果の実軸成分を極性で表わ
すと+−++−+−++とランダムの場合はデー
タと判断する。すなわち、受信信号の符号系列で
もつてトレーニング又はデータの識別が可能とな
る。 データ送信中に障害等が発生して瞬断が起つた
場合、本発明によるトレーニング検出回路を使用
すれば受信信号がデータであるかトレーニング信
号であるかが簡単に検出でき、データ受信中であ
れば瞬断が復旧した以降のデータを無効とせず継
続して有効なデータを受信できるため、瞬断耐力
向上が図れる。 (g) 発明の効果 以上、詳細に説明したように、本発明のデータ
モデム用トレーニング検出方式によれば、トレー
ニング検出回路を付加することによつてトレーニ
ング信号の検出が容易に行なえるため、受信デー
タの瞬断が復旧した以降のデータを無効とせず継
続して有効なデータを受信でき瞬断耐力を著しく
向上させ得るといつた効果大なるものである。
[Table] Segment 1 of the training signal does not contain any signal, but the transition point with segment 2 is used to detect the start of data reception. Segment 2 of the training signal consists of repetitions of two signal elements. As shown in FIG. 1, the first signal element A has a relative amplitude of 3 and defines an absolute phase reference of 180 degrees. The second signal element B changes with the data rate, (1-j) at 7200 bit/sec, 9600 bit/sec
When , there are 3 (1-j) vectors. Segment 2 is ABAB during the 128 symbol interval...
Repeat... Training signal segment 3
consists of two signal elements that vary according to an equalizer conditioning pattern, also called a PN code. The first signal element C has a relative amplitude of 3 and an absolute phase of 0°, and the second signal element D varies with the data rate, at 7200 bit/sec (-1 + j),
At 9600 bit/sec, there are 3 (-1+j) vectors. The equalizer conditioning pattern is a pseudo-random sequence, and when this sequence is 0, C occurs, and when this sequence is 1, D occurs. Furthermore, the signal of segment 4 is used to pull in the descrampler circuit. This segment 2 signal includes a demodulated carrier. That is, vectors A and B are vectors
It can be considered as the sum of A' and CAR and the sum of vector B' and CAR, and segment 2 is A, B, A, B
When iterating, the invariant component is CAR, and the alternating component is
A' and B', the sum of alternating components A' and B' is zero, and the constant component CAR is the carrier signal. Similarly, when calculating the invariant component and therefore the carrier component for segment 3, vectors C and D
are vector A′ and CAR′ and vector B′ and
Since it is the sum of CAR′, the carrier component is CAR′, which is the carrier component CAR of segment 2.
The phase is shifted by 180°. When pulling in the equalizer (automatic equalizer), the transmitting side sends out the signal of segment 3, and the receiving side also generates the same signal, and for example, compares the two to find the signal necessary for waveform correction. To carry out such an operation, it is necessary to detect the start point of segment 3 and to start generating the above-mentioned signal on the receiving side. Conventionally, when a failure occurs due to the influence of a transmission path and a momentary interruption of the receiving carrier occurs, the following two methods have been considered as methods for improving resistance to momentary interruption. That is, (a) a method in which training detection is not performed, and (b) a method in which training detection is performed have been implemented. (b) A method that does not perform training detection is a method that deals with this by extending the OFF time of the character detector. This conventional method has ideal instantaneous interruption tolerance for short instantaneous interruptions, but it is ineffective against long interruptions because of constraints on the time in the NET area. Furthermore, (b) if the training detection method is implemented, it will be effective against long instantaneous interruptions, but an offset will occur against short instantaneous interruptions. FIG. 2 is a diagram showing the characteristic relationship between the instantaneous interruption time and the error occurrence time in the conventional methods (a) and (b). (d) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a training detection method for a data modem that minimizes data that becomes invalid due to instantaneous interruptions and improves instantaneous interruption tolerance characteristics. The purpose is to (e) Configuration of the invention: a first delay circuit that delays a received signal by one signal element via a waveform shaping filter; and an adder circuit that adds an input signal that does not pass through the first delay circuit;
a second delay circuit that delays the output of the adder circuit by 180 degrees; the output of the second delay circuit is input to a multiplier circuit; and the output of the second adder circuit is input to the second delay circuit;
input to the multiplication circuit without passing through the delay circuit,
This is achieved by providing a training detection method for a data modem, characterized in that the output effect of the multiplier circuit is input to sign determination via a tapped delay element to detect whether it is a training signal or data. (f) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings. FIG. 3 is a sequence diagram of training signals used in the present invention. The contents of each of the training signal segments SEG1 to SEG4 are as explained in FIG. 1. FIG. 4 is a circuit diagram showing an embodiment of a data modem training detection method to which the present invention is applied. In the drawing, ROF is a waveform shaping filter that shapes the waveform of the input signal, T is a delay element, + is an addition circuit, × is a multiplication circuit, and CJU is a sign determination that determines whether it is training or data based on the output from the tapped delay line. Each circuit is shown below. The signal input via the communication line is first input to the waveform shaping filter ROF, noise components etc. are removed, and only the desired reception signal is received. Signal elements A and B in segment SEG2 shown in Figure 3
When inputted, the signal is passed through the waveform shaping filter ROF, delayed by one signal element at the delay element TA , and the signal A+B is extracted at the adder circuit +. A at point a
As shown in the figure, the +B vector component is only a negative imaginary component. Next, the A+B signal is a delay element
When delayed by 180 degrees at T B and complex conjugated, the A+B vector component at point b becomes only a plus imaginary component, as shown in the figure. When the A+B vector component converted to the plus imaginary component and the minus imaginary A+B vector component before conversion are multiplied by the multiplier, the A+B vector component is changed from an imaginary number to a real number, and the output is the training signal. When the real axis component is expressed in terms of polarity, the result of +++++++++++ is obtained. This output result is input to the sign determination circuit CTU from each tap of the tapped delay elements T C to T G. In the sign judgment circuit CJU, when the real axis component of the output result from the tapped delay element is expressed by polarity, if it is ++++++++++++, it is judged that the received signal is training, and the real axis component of the output result from the tapped delay element is expressed by polarity. If it is random, +-++-+-++, it is determined to be data. That is, training or data identification can be performed using the code sequence of the received signal. If a failure occurs during data transmission and a momentary interruption occurs, using the training detection circuit according to the present invention can easily detect whether the received signal is data or training signal. For example, since valid data can be continuously received without invalidating data after the momentary interruption has been recovered, resistance to momentary interruption can be improved. (g) Effects of the Invention As explained in detail above, according to the training detection method for data modems of the present invention, by adding a training detection circuit, training signals can be easily detected. This has a great effect in that valid data can be continuously received without invalidating the data after the momentary data interruption has been recovered, and the resistance to momentary interruption can be significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はトレーニング信号のアイパターン図、
第2図は従来の受信キヤリアの瞬断が起つた場合
の瞬断耐力向上方法における特性図、第3図はト
レーニング信号のタイムチヤート、第4図は本発
明によるデータモデム用トレーニング検出方式の
一実施例の回路構成図である。 図面において、A,B,C,D,Zは信号要
素、ROFは波形成形フイルタ、TA〜TGは遅延素
子、+は加算回路、×は乗算回路、CJUは符号判定
回路をそれぞれ示す。
Figure 1 is an eye pattern diagram of the training signal.
Fig. 2 is a characteristic diagram of a conventional method for improving momentary interruption tolerance when an instantaneous interruption occurs in a receiving carrier, Fig. 3 is a time chart of a training signal, and Fig. 4 is a diagram of a training detection method for a data modem according to the present invention. FIG. 2 is a circuit configuration diagram of an example. In the drawings, A, B, C, D, and Z are signal elements, ROF is a waveform shaping filter, T A to T G are delay elements, + is an addition circuit, × is a multiplication circuit, and CJU is a sign determination circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 受信信号を波形成形フイルタ経由で1信号要
素分遅延する第1の遅延回路と前記第1の遅延回
路を経由しない入力信号とを加算する加算回路
と、前記加算回路の出力を180゜遅延する第2の遅
延回路と、前記第2の遅延回路の出力を乗算回路
に入力し、一方前記第2の加算回路の出力を前記
第2の遅延回路を経由せずに前記乗算回路に入力
し、前記乗算回路の出力結果をタツプ付遅延素子
経由で符号判定回路に入力し、トレーニング信号
かデータかを検出することを特徴とするデータモ
デム用トレーニング検出方式。
1. A first delay circuit that delays a received signal by one signal element via a waveform shaping filter, an adder circuit that adds an input signal that does not pass through the first delay circuit, and a delay circuit that delays the output of the adder circuit by 180 degrees. a second delay circuit; the output of the second delay circuit is input to a multiplication circuit; while the output of the second addition circuit is input to the multiplication circuit without passing through the second delay circuit; A training detection method for a data modem, characterized in that the output result of the multiplication circuit is input to a sign determination circuit via a delay element with a tap to detect whether it is a training signal or data.
JP56213626A 1981-12-29 1981-12-29 Training detection system for data modem Granted JPS58116848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56213626A JPS58116848A (en) 1981-12-29 1981-12-29 Training detection system for data modem

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56213626A JPS58116848A (en) 1981-12-29 1981-12-29 Training detection system for data modem

Publications (2)

Publication Number Publication Date
JPS58116848A JPS58116848A (en) 1983-07-12
JPS6347306B2 true JPS6347306B2 (en) 1988-09-21

Family

ID=16642269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56213626A Granted JPS58116848A (en) 1981-12-29 1981-12-29 Training detection system for data modem

Country Status (1)

Country Link
JP (1) JPS58116848A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01269346A (en) * 1988-04-21 1989-10-26 Maspro Denkoh Corp Psk transmission and reception system
FR2714558B1 (en) * 1993-12-23 1996-03-15 Sgs Thomson Microelectronics Circuit for recognizing a sequence of words in a modem.

Also Published As

Publication number Publication date
JPS58116848A (en) 1983-07-12

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