JPS6347396B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to time switch circuits. More specifically, the present invention relates to a time switch circuit, which plays a central role in the communication path equipment of a digital exchange, as well as a space switch.

[Prior art]

As is well known, time switches are used in communication path devices of digital exchanges, and have the function of performing time-division switching by changing the temporal order of input data.

A conventional example of this type of time switch will be explained with reference to FIG. That is, the conventional time switch is composed of a call memory 1, a holding memory 2, and a counter not shown in FIG. The time order of input data is exchanged by repeating writing and reading in a fixed order using the output from the counter as an address, that is, sequential reading. Since this is realized with memory, it is suitable for LSI technology, and has rapidly developed with the recent advances in LSI technology.

However, in a switch using the above memory, the throughput of the switch is limited by the cycle time of the memory. The cycle time of memory is slower than the operating time of registers and logic gates, and the cycle time tends to increase as the storage capacity increases. On the other hand, it has been extremely difficult to improve the processing performance of conventional time switches that use larger memory capacities and shorter cycle times.

[Purpose of the invention]

It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a high throughput time switch circuit.

[Summary of the invention]

The present invention comprises: means for supplying addresses; demultiplexer means with a storage function for storing time-division multiplexed and sequentially input data in positions according to the addresses from the address supply means and outputting the stored data in parallel; means for taking in parallel data from the demultiplexer means with a storage function and sequentially outputting the data; It consists of one input terminal and multiple output terminals, a demultiplexer that inputs the input data of the input data latch to the input terminal and outputs it to the output terminal specified by the address, and an output data latch that stores the data from the output terminal. By connecting demultiplexer modules with storage function in multiple stages in a tree shape, and operating each stage as a pipeline,
It is characterized by outputting time-division multiplexed input data in a previous number that is different from the order in which it was input. An embodiment of the present invention will be described in detail below with reference to the drawings.

[Embodiments of the invention]

FIG. 2 shows an example of the basic configuration of the present invention, and shows a four-time multiplex time switch circuit. In Figure 2, 11
12 is a 4-stage shift register, and 13 is a holding memory. The holding memory 13 uses the address ADR as the clock pulse CLK.
The data is supplied to the demultiplexer with storage function 11 in synchronization with the data. The demultiplexer with memory function 11 includes an input data latch 11-1 and a demultiplexer 11.
-2 and latch 11-3. The time division multiplexed input data D _io is input to the input data latch 11.
-1 and stored in latch 11-1. Demultiplexer 11-2 is connected to latch 11-1.
The data stored in the output terminals #1 to #4 are
It outputs to the output terminal specified by the address ADR from the holding memory 13, and puts the unspecified output terminal into a high impedance state. Demultiplexer 11
-2 is stored in latch 11-3. The shift register 12 has a latch 11-3.
It takes in the stored data in parallel and sequentially outputs it in series as output data D _put . Input data latch 1
1-1, latch 11-3, and holding memory 13 are operated by clock pulse CLK, and shift register 12
takes in the data stored in latch 11-3 with a frame pulse FP having a period four times that of clock pulse CLK, and shifts out the data with clock pulse CLK.

FIG. 3 is a timing chart explaining the operation of FIG. 2. In the frame shown in FIG. 3, the input data D _io of B1 to B4 are input to the input data A1 to A4 taken into the shift register 12 in the previous frame.
Then, 1 every clock pulse CLK.
The data are sequentially input to the input data latch 11-1 one by one. In this frame, the holding memory 13 outputs addresses ADR as #3, #1, #4, and #2 in accordance with the clock pulse CLK. According to this address ADR, the demultiplexer 11-
2 sequentially outputs input data B1, B2, B3, and B4 to output terminals #3, #1, #4, and #2 of the demultiplexer according to this address ADR, and stores the corresponding locations of latch 11-3. . Therefore, in this frame, writing of data B1 to B4 and reading of the previous frame are executed simultaneously. Data B1 to B4 stored in the latch 11-3 are taken in parallel to the shift register 12 by the next frame pulse FP. #1 of shift register 12,
#2, #3, #4 have data B2, B4, B1,
B3 is set, and in parallel with the next frame data being input to _Dio by CLK, B2,
B4, B1, and B3 are sequentially shifted out as output data D _put .

FIG. 4 shows an embodiment of the present invention that is an extension of FIG. 2, and shows an example of a 12-multiplex time switch circuit. In this embodiment, the number of bits of data will be explained as 1 bit, but if the data is 8 bits, it is sufficient to provide 8 circuits shown here, and the present invention can be applied to data with any number of bits. Needless to say.

In FIG. 4, 21 is a 1-bit latch, 2
2 is a 3-output demultiplexer that outputs input data to one of three output terminals according to a control signal and puts the other output terminal in a high impedance state; 23;
31 outputs the input data to either of two output terminals according to the control signal when the signal at the enable signal input terminal E is "H", puts the other one in a high impedance state, and connects the enable signal input terminal E.
A two-output demultiplexer which puts all output terminals in a high impedance state when the signal of
It consists of one stage and two bits of the same circuit.
41 is a 12-bit latch, and 42 is a 12-stage shift register. 43 is a shift register for one stage, 44
is a two-stage shift register, which also provides a delay to the control signal when the demultiplexer is pipelined. 45 is a 2-bit decoder, and 46 and 47 are 1-bit decoders. 4
8 is a circular shift register, which has the function of a holding memory for storing random addresses.
49 to 52 are AND gates.

The latch 21 takes in input data Din in accordance with the clock pulse CLK1 and outputs it to the three-output demultiplexer 22. 3 output demultiplexer 2
2 is the latch 2 according to the control signals S11 to S13.
The input data from 1 is output to any of the three output terminals 01 to 03. This output is clock CLK.
1 and are taken into registers 32 to 34 that operate according to 1. The register 32 has a demultiplexer 22
At the same time as the output from output terminal 01, a control signal S11 for selecting output terminal 01 is taken in. Similarly, the registers 33 and 34 also receive selection signals S12 and S indicating that the output terminals are selected simultaneously with the data of the output terminals 02 and 03 of the demultiplexer 22, respectively.
13 is imported. Each two outputs of registers 32-34 are connected to two-output demultiplexers 23-25.
is connected to each input terminal D, E of. The demultiplexers 23 to 25 each have a common control signal S21, S2.
2, the data at the input terminal D is output to one of the two output terminals 01 and 02, and the other output terminal is set to high impedance. It is executed when the signal is “H”, and when it is “L”,
Both 01 and 02 are in a high impedance state. The outputs of the demultiplexers 23-25 are connected to the registers 35-40 which are driven by the clock CLK1.
are stored respectively. The register 35 takes in the data at the output terminal 01 of the demultiplexer 23, and at the same time inputs the demultiplexer enable signal S11'.
The output of the AND gate 49 which performs the logical product of and the control signal S21 is taken in. The register 36 takes in the data at the output terminal 02 of the demultiplexer 23, and at the same time performs an AND operation of the enable signal S11' of the demultiplexer 23 and the control signal S22.
Take in the output of gate 50. The register 37 takes in the data at the output terminal 01 of the demultiplexer 24, and at the same time takes in the output of the AND gate 51 which takes the AND of the enable signal S12' of the demultiplexer 24 and the control signal S21. The register 38 takes in the data at the output terminal 02 of the demultiplexer 24, and at the same time takes in the output of the AND gate 52 which takes the AND of the enable signal S12' of the demultiplexer 24 and the control signal S22.
Register 39 is output terminal 0 of demultiplexer 25.
At the same time, the enable signal S13' of the demultiplexer 25 and the control signal S21 are taken in.
The output of the AND gate 53 is taken in to take the logical product. The register 40 takes in the data at the output terminal 02 of the demultiplexer 25, and at the same time takes in the output of the AND gate 54 which takes the AND of the enable signal S13' of the demultiplexer 25 and the control signal S22. The data stored in each of registers 35-40 and the enable signal are supplied to data inputs D and enable signal inputs E of demultiplexers 26-31. These demultiplexers 26 to 31 share a common control signal S31, S32.
Accordingly, the data at the data input terminal D is output to one of the two output terminals 01 and 02, and the other output terminal is set to high impedance. is executed when the signal is “H”, and when it is “L”, it is 0
1 and 02 are both in a high impedance state. The outputs of the demultiplexers 26 to 31 are
12 bits are taken in parallel and held in latch 41 driven by clock CLK1. A 12-stage shift register 42 simultaneously takes in the data of the latch 41 in 12 stages according to the frame pulse FP, shifts it to the next stage according to the clock CLK1, and outputs the data.
This is a well-known shift register that outputs Dout.
The circular shift register (holding memory) 48 includes:
Twelve pieces of 4-bit address information specifying any stage of the 12-stage shift register 42 are stored in arbitrary order, and this address information is
It is output sequentially according to CLK1. This address consists of three partial addresses A1 (2 bits), corresponding to the three pipeline stages of the demultiplexer.
It is divided into A2 (1 bit) and A3 (1 bit). The highest partial address A1 is decoded by the decoder 45 into three control signals S11 to S13,
The signal is supplied to the first stage demultiplexer 22. The next digit partial address A2 is the clock pulse CLK.
decoder 4 via a register 43 driven by
6, and supplied to the second stage demultiplexer group 23-25 as control signals S21 and S22 one clock pulse after A1. The lowest partial address A3 is decoded by the decoder 47 via a two-stage shift register driven by the clock pulse CLK1, and after one clock pulse from A2, the third address is output as the control signals S31 and S32.
The demultiplexers 26-31 of the stage are supplied.

FIG. 5 is a timing chart for explaining the operation of FIG. 4. Frame pulses EP indicate frame divisions, and each frame takes in 12 pieces of data and takes out the 12 pieces of data that were taken in the previous frame from the shift register. Data b1 between 1 and 12 of CLK1
~b12 are sequentially taken into the latch 21 (fifth
Figure _Dio ). Similarly, data c1 between 13 and 24 of CLK1
~ c12, d1 to d12 between 25 and 36 of CLK1
is taken in. On the other hand, an address for writing data is sent from the holding memory 48 in synchronization with CLK1. For example, data b1 to b1 are generated during 12 cycles from the 12th cycle of CLK1.
Random addresses bA to bL for writing 2 are sent. Focusing on bA among these addresses, first, the decoded signals S11, S12, S13 of the most significant part address bA1 are input to the demultiplexer 22, and data b1 is outputted to the output terminal selected by this signal. That is, four stages of the 12 stages of shift registers to be finally written are selected. Therefore, for example, S11=
When output terminal 01 is selected with H, S12=L, and S13=L, data b1 and S1 are stored in the register 32.
1=H is taken in. At this time, register 33,
34 enable signal storage section contains S12=S1
3=L is captured. Since the output terminals 02 and 03 of the demultiplexer 22 are in a high impedance state, the data storage portions of the registers 33 and 34 that receive these output terminals retain their previous values. partial address
After bA2 is delayed by one clock, it is supplied to the decoder 46 and becomes decoded S21 and S22. Among the demultiplexers 23 to 25 that receive this signal, S1 whose enable signal is "H"
Only the demultiplexer 23 supplied with S12' and S13' whose enable signal is "L" executes a multiplexer operation, and the demultiplexers 24 and 25 supplied with S12' and S13' whose enable signal is "L" have high impedance output terminals. state. Therefore, the data storage portions of registers 35 to 40 include register 35 connected to the output of demultiplexer 23.
Data is supplied only to registers 37 to 36, and no data is supplied to the remaining registers 37 to 40, so that the previous data is held. Further, since the AND of the enable signal and the control signal is input to the enable signal storage section, "L" is stored in the registers 37 to 40 in which the enable signal S11' is "L". For example, control signal S21=“H”, S22=
By “L”, the output terminal of the demultiplexer 23 is 0.
When 1 is selected, data is output to 01, and 0
2 is high impedance. Further, the output of the AND gate 49 becomes "H" and the output of the AND gate 50 becomes "L". Therefore, data and an enable signal "H" are stored in the register 35, and an enable signal "L" is stored in the register 36. Therefore, the shift registers to be written to are narrowed down to the two stages selected by the partial addresses bA1 and bA2 at this point. The lowest part address is further delayed by one clock and then supplied to the decoder, and the decode signal S3 is sent to the decoder.
1, S32. Of the demultiplexers 26 to 31 that receive this signal, the one to which "H" is supplied as an enable signal is the demultiplexer 2.
6, this is the control signal S31, S3
2, and the outputs of the other demultiplexers 27 to 31 become high impedance. Therefore, for example, S31="H", S32
="L" output terminal 01 is selected, input data is output to 01. At this time, only 1 bit supplied with this data is written into the 12-bit latch 41, and the remaining 11 bits are supplied with a high impedance state, so that they retain their previous values.
In this way, one stage determined by the partial addresses bA1, bA2, and bA3 is selected, and input data is written there.

The above operations are performed continuously for addresses bB...bL, and in the next frame, they are sequentially output from the shift register. Due to the pipelining of the demultiplexer, writing of random addresses is performed in parallel at the same period as the output of data from the shift register 42. Moreover, since the data output from the shift register 42 is equivalent to sequential read, the time switch function by random write and sequential read is obvious.

In the embodiment shown in FIG. 4, each bit of the 2-bit wide registers 32 to 40 used for pipeline processing has the same function as one stage of shift registers, and is clocked with an opposite phase. It consists of two working latches. That is, while the first stage latch is taking in data, the second stage latch holds the data that has already been taken in. If this front-stage latch is regarded as the front-stage demultiplexer, and the rear-stage latch is regarded as the storage function of the latter-stage demultiplexer, each demultiplexer becomes a circuit module of the same configuration with a latch at each of its input and output ends. For example, a demultiplexer module with a storage function consisting of a latch after the demultiplexer 23 and the register 32 and a latch before the registers 35 and 36; a demultiplexer module with a memory function, and latches and registers 39 and 40 after the demultiplexer 25 and register 34;
The demultiplexer module with storage function consisting of the front and rear latches is the same circuit module. The example shown in Figure 4 shows a three-stage pipeline demultiplexer configured in a tree shape, but when realizing a larger-scale switch, the number of pipeline stages increases, and many of the circuit modules described above are used. be done. Further, the first stage demultiplexer 22 includes a latch 21 and registers 32 and 3.
The front-stage latches 3 and 34 form a demultiplexer with a memory function. In this case, the input side latch is only a data latch, and the output side latch has a 2-bit configuration for data and enable signal storage. Further, in the final stage demultiplexer, for example, in 26, the input side latch is the register 3.
It is a latter-stage latch of latch 41, and has a 2-bit configuration for storing data and an enable signal, and the output side latch is a demultiplexer with a storage function consisting of 2 bits of latch 41.

FIG. 6 shows an example of a circuit in which the demultiplexer is constructed of MOS transistors, taking the demultiplexer 23 as an example. It can be configured with transfer gates, so
It consumes no power, has a small number of elements, and operates at high speed.

Further, as an example of a demultiplexer module with a memory function, as shown in FIG. 7, which includes a demultiplexer 23 and latches before and after the demultiplexer 23, the module is composed of latches 71 to 73.
This can also be realized by controlling the signal to the clock input terminal of No. 3 with a control signal and an enable signal.

According to the embodiment described above, since the random write is performed by the pipeline demultiplexer including the register and the demultiplexer, all operations are performed at approximately the operating speed of the shift register. This is extremely fast compared to memory cycle times. Moreover, since writing and reading can be performed simultaneously, the number of cycles required is half that of a memory in which writing and reading are performed separately. Furthermore, since data is written to memory circuits such as registers and latches every cycle, dynamic circuits can be used. Therefore, it can be realized with a small number of elements and low power consumption. Moreover, it can be realized by repeatedly arranging small-scale multiplexer modules, making it easy to design and allowing for high-density integration, making it suitable for LSI. That is, it simultaneously achieves high speed and large scale, which is impossible with conventional memories, and has the advantage of promoting miniaturization, low power consumption, and economicalization of digital exchanges.

〔Effect of the invention〕

As described above, according to the present invention, the output from the demultiplexer with storage function and the shift register is performed in parallel, so that a time switch circuit with high throughput can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example, FIG. 2 is a diagram showing an example of the basic configuration of the present invention, FIG. 3 is a timing chart explaining FIG. 2, and FIG. 4 is a diagram showing an embodiment of the present invention. , FIG. 5 is a timing chart explaining FIG. 4, FIG. 6 is a diagram showing a circuit example of the demultiplexer shown in FIG. 4, and FIG. 7 is a diagram showing an example of the configuration of the demultiplexer module with memory function shown in FIG. FIG. 11...Demultiplexer with memory function, 12...
...Shift register, 13...Holding memory.

Claims (1)

[Scope of Claims] 1. A demultiplexer with a storage function that includes means for supplying an address, and a demultiplexer with a storage function that stores time-division multiplexed input data at a position according to the address from the address supply means and outputs the stored data in parallel. and a means for taking in the parallel data output from the demultiplexer with storage function and sequentially outputting the data, and outputting the time-division multiplexed input data in a different order from the input order. The demultiplexer with storage function is comprised of an input data latch for sequentially storing time division multiplexed input data, one input terminal and multiple output terminals,
A tree-shaped demultiplexer module with multiple memory functions consists of a demultiplexer that inputs the input data of the input data latch to the input terminal and outputs it to the output terminal specified by the address, and an output data latch that stores the data from the output terminal. A time switch circuit characterized in that it is configured by connecting in multiple stages, and each stage operates in a pipeline.