JPS6348119B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor read-only memory (hereinafter referred to as ROM) with an added data security function. In recent years, with the development of microcomputers, the use of ROM has expanded to a wide range of uses, and in particular, ROM is often used to store system operation programs. By the way, developing this operation program usually requires a huge amount of man-hours, and it is necessary to protect it as an important secret.
When an operation program is stored in a conventional ROM, the stored contents are stored in the ROM.
It is more easily readable and the operating program is difficult to protect as a secret. SUMMARY OF THE INVENTION An object of the present invention is to provide a ROM in which it is difficult to read normal data and can protect the confidentiality of stored data. The ROM according to the present invention includes an address detection circuit for selecting a specific address with respect to a conventional ROM, and a logic conversion that inverts the logic of the output of the ROM by the output of the address detection circuit when the specific address is selected. It is characterized by being equipped with a circuit. The present invention will be explained below using examples. This embodiment uses address signals A ₀ , A ₁ , . . . as shown in FIG. 2, in contrast to the conventional ROM shown in FIG.
According to An, a logic conversion circuit which has an address detection circuit for selecting a specific address and inverts the logic of the ROM output by the output signal φ ₁ of the address detection circuit is connected in series between the Y selector 5 and the output buffer 6. It is connected. As shown in FIG. 3, in the address detection circuit, the code setting unit 9 selects a specific address using the address signals a ₀ , a ₀ , a ₁ , a ₁ , ...a _o , a _o input from the address input buffer 1. NOR gate Q ₁ when
is set so that the output φ ₁ of is set to “H” level,
The output φ ₁ is input to a logic conversion circuit. The code setting section can be easily set using a contact process mask, an aluminum process mask, etc. during the manufacturing process. As shown in FIG. ₄ , the logic conversion circuit converts the output Q,
Transfer gates T ₁ , T ₂ controlled by Q
Accordingly, the output signal D can be inverted or non-inverted with respect to the input signal d of the logic conversion circuit, and the logic of the output of the ROM can be set to positive logic or negative logic. . Therefore, when the specific address set by the code setting section is selected, the logic of the output of the ROM is converted from positive logic to negative logic, or vice versa, so that the specific address If you try to read the data stored in ROM without distinguishing it from other addresses, the logic of the ROM output after selecting the specific address is as follows.
Since the data is reversed, incorrect data will be read. In other words, the confidentiality of the data stored in the ROM is protected. In addition, by setting the specific address to the selected state, the output of NORQ ₂ will always be at the "L" level, so it is possible to know whether the logic of the ROM output is positive logic or negative logic. If the data in the ROM is read out while taking into account not to select the specific address, the correct data stored in the ROM can be read out. As explained above, according to the present invention, the conventional ROM
By providing an address detection circuit and a logic conversion circuit that converts the logic of the output of the ROM based on the output of the address detection circuit, it is possible to provide a ROM that can protect the confidentiality of stored data.

[Brief explanation of drawings]

FIG. 1 is an example of a block diagram showing the configuration of a conventional ROM, FIG. 2 is a block diagram showing the configuration of the ROM of the present invention, FIG. 3 is a diagram showing an example of an address detection circuit, and FIG. FIG. 3 is a diagram showing an example of a logic conversion circuit. 1...Address input buffer, 2...Medecoder, 3...Y decoder, 4...Memory cell array, 5...Y selector, 6...Output buffer,
7...Address detection circuit, 8...Logic conversion circuit,
9...Code setting section, _Q1 , _Q2 ...NOR gate,
Q ₃ ... inverter gate, T ₁ , T ₂ ... transfer gate, FF1 ... flip-flop.

Claims (1)

[Claims] 1. Equipped with a memory cell array, an address detection circuit that detects selection of a specific address for each address signal, and a logic conversion circuit that selectively converts the logic of an external output signal depending on the content of the output signal of the address detection circuit. According to the content of each output signal of the address detection circuit, the logic conversion circuit sets a first state in which the logic of the output from the memory cell array is inverted, and a first state in which the logic of the output from the memory cell array is inverted. and a second state that is a non-inverted state.