JPS6348120B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory that can improve reliability.

Generally, a MOS field effect transistor (MOS FET) having a floating gate structure is widely used as a nonvolatile semiconductor memory. Figure 1a
1 shows a cross-sectional configuration diagram of this memory cell, and FIG. 1B shows its symbol diagram. That is, on a P-type semiconductor substrate, N ⁺ type diffusion parts 11 and 12 are arranged as a source,
Provided as a drain. Then, a two-layer gate structure is provided on this substrate, in which an electrically insulated floating gate 13 is provided, and a control gate electrode 14 for controlling the power flowing to the memory cell is further provided on this floating gate 13. are doing. and,
This memory cell becomes conductive at a low control gate potential when the floating gate is in a neutral state, and does not apply a high potential to the control gate electrode when electrons are injected into the floating gate. There is no continuity. This situation is shown in figure c, where the characteristics are shown by solid line 15 when the floating gate is in a neutral state and solid line 16 when electrons are injected. Therefore, "0" and "1" information can be stored in the memory cell depending on whether electrons are injected or not. To inject electrons into the floating gate, a high voltage (for example, 20V) can be applied to the control gate and drain. Of the electron-hole pairs generated by impact ionization near the drain, electrons are injected into the floating gate.

FIG. 2 is a block diagram of a semiconductor memory using such a memory cell. That is, a plurality of row lines R ₁ to _{R n} specified in one direction, and
Multiple column lines set perpendicular to this row line
Memory cells M ₁₁ to _{M no} are arranged corresponding to each intersection position set by S ₁ to S _o . The row lines control switching of memory cells using control signals from the row decoder, and the column lines control switching of column gate transistors G ₁ to G _o using signals C ₁ to _{C o} supplied from the column decoder to control the switching of memory cells in the memory cells. Reading information or writing information to memory cells. Furthermore, the column gate transistors G ₁ to G _o are commonly connected, and the write power supply is connected to the drain of the memory cell.
Write transistor to supply V _p
Tr ₁ is provided, and this transistor is
Tr ₁ is controlled by switching. A high voltage or 0V is applied to the gate of the transistor _Tr1 depending on the data "0" or "1" state. That is, when writing data, the signal D is set to a high voltage (for example, 20 V) while 20 V is applied to V _p . Then, a memory cell is selected by the row line and column gate transistors selected by the row and column decoders, and when a high voltage is applied to the drain and gate of this memory cell, electrons are injected into the floating gate and write is performed. will be carried out. Furthermore, the nodes where the column gate transistors are commonly connected
A memory power supply circuit composed of transistors Tr ₂ to _{Tr 5} is provided at N ₁ . This circuit is a power supply
A predetermined potential is extracted from the common connection point of transistors Tr ₄ and Tr ₅ inserted in series between V _C and the ground point V _S , and is supplied to the gates of transistors Tr ₂ and Tr ₃ to raise the drain potential of the memory cell. It is kept at a potential lower than the power supply V _C. This is because if the drain voltage of the memory cell is high when reading data, electrons will gradually be injected into the floating gate, which was in a neutral state, over long periods of use.
This is to prevent data from being inverted due to these electrons.

A depletion type transistor Tr ₆ serving as a load element is provided between the transistor Tr ₃ and the inverter 17 , and a power supply V _c is supplied to the column line potential V _A supplied to the gate of the transistor Tr ₈ .
(Signal read from memory cells _M11 to _Mno )
The amplitude of the signal is increased. and transistor
Tr ₈ is controlled to be conductive, and the output signal OUT of the inverter 17 is supplied to the subsequent output buffer circuit.

The operation of the semiconductor memory will be explained by taking data reading as an example. For example, if C ₁ is selected by row line R ₁ and column decoder, transistor G ₁ becomes conductive and memory cell M ₁₁ is selected. Here, if the floating gate of the memory cell is in a neutral state, the memory cell _M11 is conductive, the column line is discharged, and its potential is supplied to the inverter 17 . The output of the inverter 17 becomes "1" and is transmitted to the output buffer circuit. Furthermore, when electrons are injected into the floating gate of memory cell _M11 , memory cell _MA1 is turned off, the column line is charged by transistors _Tr2 and _Tr6 , and the output of inverter 17 becomes "0". .

In this type of semiconductor memory, in order to detect the column line potential that changes depending on the on/off state of the memory cell, sufficient electrons are injected into the memory cell so that the threshold voltage V _th of the memory cell exceeds the power supply potential V _c . It must be rising. For example, if the threshold voltage V _th of a memory cell has increased to 5V, the column line will be charged to "1" when the row line potential is below 5V, and when the row line potential is above 5V, the column line will be charged to "1". Discharged to "0". The row line potential is normally proportional to the power supply potential, so if the power supply is used at 4.5V to 5.5V,
The threshold voltage V _th of the memory cell must be maintained at 5.5V or higher. In this way, the threshold voltage of the memory cell
V _th must be set sufficiently high.

By the way, in such a semiconductor memory circuit,
In a memory testing process, those with defective memory cells can be removed. That is,
For example, the threshold voltage V _th of a given memory cell is 7V
Suppose that it is written in . Here, the power supply voltage is
If the voltage is set to 7V or more, the potential of the row line also rises correspondingly, so the memory cell turns on and the column line goes to "0". Therefore, it can be seen that the threshold voltage V _th of this memory cell is 7V. In this state, various tests are performed, including exposing the memory to high temperatures. Thereafter, the power supply potential is increased to check whether this memory cell is good or not. For example, if the memory cell is turned on at 6V and the column line potential becomes "0", this means that electrons have escaped from the floating gate, indicating that there is a problem with the insulation of the floating gate. Therefore, such semiconductor memories cannot be shipped.

FIG. 3 shows a circuit in which a circuit consisting of transistors Tr ₉ to Tr ₁₁ is added to the common connection point N ₁ of the column gate transistors _{of the} semiconductor memory shown in FIG. Its role is to suppress the amplitude of the column line potential and increase the read speed. In other words, a transistor that is installed between the power supply V _c and the ground point V _s and works as an inverter.
The potential at the connection point of Tr ₉ and Tr ₁₀ is changed to the potential at the connection point of Tr 9 and Tr ₁₀
The power source V c is supplied to the gate of the column gate transistor to control conduction, and the power supply V _c is supplied to the common connection point (node N ₁ ) of the column gate transistors.

According to such a configuration, when the potential of the node _N1 decreases, the conduction resistance of the transistor _Tr10 increases, the gate potential of the transistor _Tr11 increases, and the conduction resistance of the transistor _Tr11 decreases. Therefore, it is possible to prevent the potential of the node _N1 from dropping too much, and it is possible to increase the read speed.

Incidentally, in this circuit as well, it is possible to test the quality of the memory cells in the same manner as in the semiconductor memory circuit shown in FIG.

The circuit shown in FIG. 4 is a semiconductor memory constructed using differential sense amplifiers in order to reduce the amount of data written to memory cells and increase the read speed. That is, the signal read from the memory cell is supplied to one input terminal of the differential sense amplifier RA. This differential sense amplifier RA is composed of transistors Tr ₁₂ to Tr ₂₀ , and its output is determined by the potential difference between nodes A and B. If the potential of node A is V _A and the potential of node B (output of comparison potential generation circuit V _M ) is V _B , if V _A > V _B , the output is "1", and if V _A < V _B , the output is "1". Output is "0"
become. If the gate potential of transistor M' is V _R , the potential at node B is such that the floating gate is in a neutral state,
In other words, when a memory cell to which no writing has been performed is selected, the potential at node A becomes the same as the potential at node A when the row line potential reaches _VR .

Here, if R ₁ and R ₂ are set so that V _R is 60% of V _C , that is, V _R = 0.6V _C , the selected row line becomes approximately V _C , so writing is not performed. If a memory cell that is not available is selected, V _A < V _B and the output becomes "0". If a memory cell in which writing is being performed is selected, V _A > V _B and the output becomes "1".

Next, calculate how many volts the threshold voltage of the memory cell must reach to indicate that writing has been performed. Since the memory cells M ₁₁ to _{M no} are transistors equivalent to M', their currents are proportional to (gate voltage - threshold voltage V _th ). In order for V _A > V _B , the following formula should be satisfied.

V _C −V _TM <V _R −V _TM ′ ...(1) Here, V _TM : Threshold voltage of memory cell V _th V _TM ′ : Threshold voltage of transistor M′ V _th V _R =0.6 If V _C , then V _C −V _TM ＜0.6V _C −V _TM ′ V _TM ＞0.4V _C +V _TM ′ ...(2) If V _C = 5.5V and V _TM ′ = 1.5V, The threshold voltage V _th of the memory cell is V _TM >3.7, that is,
If 3.7V or more is written, it is determined that it has been written. Therefore, it can be seen that a smaller amount of writing is required compared to the circuits shown in FIGS. 2 and 3.

FIG. 5 schematically shows the circuit shown in FIG. 4, and CV is a circuit that generates a control voltage _VR to control the transistor M' of the comparison potential generation circuit V _M.

Figures 6a to 6c show the above V _R generation circuit CV, respectively.
Figures a and b show various examples of V _C
Figure c is a circuit that generates V _R at a constant rate of V C, and generates a value that is a constant potential lower than V _C.

In the above equation (1), V _R =V _C −α, where α=
If it is 2V, then V _C −V _TM <V _C −α−V _TM ′ V _C −V _TM <V _C −2−1.5 V _TM >3.5. Therefore, in this V _R generation circuit, writing has been performed if the V _th of the memory cell exceeds 3.5V, regardless of V _C . That is, if the circuit shown in FIG. 6c is used as the V _R generating circuit, the amount of data written to the memory cell may be small. However, in the test process as shown in the circuits of FIGS. 2 and 3, it is not possible to determine whether the memory cell is good or bad. That is, even if the threshold voltage V _th of the memory cell changes, if the threshold voltage of the memory cell is maintained at 3.5V or higher, it will not be detected even if VC is changed, and a defective memory cannot be removed. Figure 6 a, b
The same can be said for the V _R generation circuit shown in .

For example, when V _TM is 5.5V, calculate the value of V _C to invert the data. V _C can be calculated by reversing the inequality sign in equation (2). Therefore, V _TM <0.4V _C +V _TM ′. If V _TM =5.5V and V _TM '=1.5V, then 5.5<0.4V _C +1.5 V _C >10.0. In other words, data cannot be inverted unless V _C is set to 10V or higher. Applying such a high voltage is undesirable because not only will a circuit designed for 5V not work properly, but there is also the risk of destroying the transistor.

As mentioned above, in the circuits shown in FIGS. 2 and 3, when writing to a memory cell,
It is necessary to perform sufficient writing, and it is necessary to raise the threshold voltage of the memory cell to a considerably high threshold voltage V _th . However, defective memory cells can be discovered by changing the power supply during the testing process.
On the other hand, in the semiconductor memory circuit shown in FIG. 4, although the amount of data written to the memory cells may be small, it has the disadvantage that defective memory cells cannot be discovered during the testing process.

This invention was made in view of the above-mentioned circumstances, and its purpose is to allow a small amount of data to be written to a memory cell, to detect defective memory cells during the testing process, and to provide reliability. An object of the present invention is to provide a nonvolatile semiconductor memory with high performance.

An embodiment of the present invention will be described below with reference to the drawings.

Figure 7 shows the V _R generation circuit.The output V _R is kept almost constant even if the power supply V _C is changed during testing, and the potential of the output V _R is raised during normal readout compared to during testing. This is how it was done. That is, a depletion type transistor _Tr21 is provided between the power supply V _C and the _VR output terminal, and its gate is connected to the _VR output terminal. Furthermore, this
Enhancement transistors Tr ₂₂ to _{Tr 25} are connected in series between the V _R output terminal and the ground point V _S .
The gate of the transistor _Tr22 has a signal R/
is supplied, and the gates of transistors Tr ₂₃ to Tr ₂₅ are connected to their respective drains. Also, V _R
Enhancement type transistors Tr ₂₆ to _{Tr 28} are connected in series between the output terminal and the ground point V _S , the gate of the transistor Tr ₂₆ is supplied with the signal /T, and the gates of the transistors Tr ₂₇ and Tr ₂₈ are connected to each other. It is connected to the drain.

In such a configuration, the signal /T is set to "1" during testing, and set to "0" during normal reading. The signal R/ is an inverted signal of the signal /T, and is set to "0" during testing and "1" during normal reading.
Therefore, during testing, the transistor Tr ₂₆ is turned on and the transistor Tr ₂₂ is turned off. Transistor during normal readout
Tr ₂₂ is turned on and transistor Tr ₂₆ is turned off. Therefore, during testing, the output potential V _R of this circuit is the sum of the threshold voltage V _T27 of the transistor Tr ₂₇ and the threshold voltage V _T28 of the transistor Tr ₂₈ , that is, "V _R = V _T27 + V _T28 ”, and during normal readout, the output potential V _R is equal to each threshold voltage of transistors Tr ₂₃ , Tr ₂₄ , and Tr ₂₅
The sum of V _T23 , V _T24 , and V _T25 , "V _R = V _T24 + V _T25 + V _T26 "
becomes. In this way, the output potential V _R is determined by the threshold voltages of the transistors Tr ₂₃ to _{Tr 25} and Tr ₂₇ and Tr ₂₈ , and is almost independent of the power supply V _C.

Below, we will examine how many volts the power supply V _C needs to be during the test to invert the data. For example, "V _TM = 5.5V", "V _R = V _T27 + V _T28 = 2V", "V _TM '=
1.5V'', the inequality sign in equation (1) above is reversed and each numerical value is substituted, and the following equation is obtained.

V _C −5.5＞2−1.5 Therefore, “V _C >6.0” and the power supply V _C
Data is inverted above 6.0V. For example, when _VR is set to 2V during testing, data is inverted when V _TM is 7V and V _C is 7.5V or higher. After performing various reliability tests, if V _TM drops to 6V, the data should invert when V _C exceeds 6.5V. Therefore, with such a configuration, memory defects can be discovered at a relatively low power supply voltage V _C in the test process.

On the other hand, during normal reading, if, for example, "V _TM =5.5V", "V _R =3V", and "V _TM '=1.5V", the data is inverted when the power supply V _C is 7V or higher. Here, if V _R is 3V, let's examine how many volts or more the threshold voltage of the memory cell needs to be to determine that data has been written. Substituting this condition into the above equation (1) results in the following equation.

V _C = V _TM <3−V _TM ′ V _TM ＞V _C −3+V _TM ′ In the above equation, if “V _C = 5.5V” and “V _TM ′=1.5V”, the threshold value of the memory cell The voltage becomes V _TM >4. Therefore, when the power supply V _C is 5.5V, if 4V or more is applied to the memory cell, it is determined that data has been written.

As described above, according to such a configuration, the second
Information can be written with a smaller amount of writing than the circuits shown in FIG. 3 and FIG. 3, and defective memory cells can be easily found by changing the power supply voltage during testing.

FIG. 8 shows another embodiment of the present invention, in which transistors Tr _{23 to} Tr ₂₅ and Tr ₂₇ to Tr ₂₈ in FIG.
It is equipped with Tr ₃₃ . this transistor
Tr ₂₉ to _{Tr 33} are transistors having the configuration shown in FIG. 1, with the control gate 14 and floating gate 13 shorted.

According to such a configuration, the transistor Tr ₂₉
~The threshold voltage of Tr ₃₃ has a one-to-one correspondence with the threshold voltage of the memory cell, so “V _R −V _TM ′”
is almost constant and does not depend on changes in the threshold voltage of the memory cell. In this case, normal enhancement type transistors may be provided as the transistors Tr ₂₉ to _{Tr 31} used during normal reading.
Furthermore, in FIGS. 7 and 8, the number of each transistor may of course be set depending on the value of the required output potential _VR .

FIG. 9 shows still another embodiment of the present invention, in which transistors Tr ₂₁ and Tr ₃₄ to _{Tr 36} are connected in series between the power supply V _C and the ground point V _S. The transistors Tr ₃₄ and Tr ₃₅ are of the enhancement type, and their gates are connected to their respective drains, and the transistor Tr ₃₆ is of the depletion type, and the signal /T is supplied to its gate.

In such a configuration, when the signal R/T is set to "1" during a test, the transistor Tr ₃₆ is turned on and the conduction resistance becomes small, and the output potential V _R becomes equal to that of the transistors Tr ₃₄ and Tr ₃₅ . This is the sum of the threshold voltages V _T34 and V _T35 . If the signal /T is set to "0" during normal readout, the transistor Tr ₃₆
The conduction resistance increases, and the output potential V _R can be set to a higher value than during the test.

Note that this invention is not limited to the above embodiments, and can be implemented _with various modifications.
Any circuit may be used as long as it sets the output potential of the generating circuit to predetermined potentials during normal reading and during testing.

As explained above, according to the present invention, the output potential V _R can be changed during testing and normal readout, so the amount of information written can be small, and the power supply V _C can be changed during testing to detect defects. Since memory cells can be discovered, highly reliable nonvolatile semiconductor memory can be obtained.

[Brief explanation of the drawing]

Figures 1a to 1c each have a floating gate structure.
A cross-sectional configuration diagram of a MOS type field effect transistor, its symbol diagram, and characteristic diagram. Figures 2 to 4 are circuit diagrams showing conventional nonvolatile semiconductor memories, and Figure 5 is a schematic diagram of the circuit shown in Figure 4 above. The figures shown in Figure 6, a to c, are the V _R of Figure 4 above, respectively.
A circuit diagram showing a generation circuit and a circuit diagram showing a modification thereof, FIG. 7 is a diagram showing a _VR generation circuit of a nonvolatile semiconductor memory according to an embodiment of the present invention, and FIG.
9 are circuit diagrams showing other embodiments of the present invention. R ₁ ~ _{R n} ... Row line, S ₁ ~ _{S o} ... Column line, M ₁₁ ~
M _no ...Memory cell, RA...Differential sense amplifier, V _M ...Comparison potential generation circuit.

Claims (1)

[Claims] 1. A memory cell arranged corresponding to each intersection position set by a plurality of row lines and a plurality of column lines, a differential sense amplifier to which one input signal is supplied from the column line, and this differential sense amplifier. A comparison potential generation circuit supplies the other input signal of the type sense amplifier and has a transistor equivalent to the transistor used in the memory cell, and a first potential is applied to the gate of the transistor equivalent to the transistor used during normal operation. The gate potential of the equivalent transistor used during the test is a second potential that is lower than the first potential and is not affected by fluctuations in the power supply voltage, and the gate potential of the equivalent transistor used during the test is 1. A nonvolatile semiconductor memory comprising: a potential supply means for supplying a potential corresponding to fluctuations in power supply voltage to a gate.