JPS6348172B2 - - Google Patents

Abstract

A laminated ceramic sheet printed circuit carrier (1) for supporting semiconductor integrated circuit chips (11) has a coefficient of thermal expansion matched to that of the chips (11) as well as a high value of capacitance. The carrier (1) provides both mechanical and electrical connections to the chip (11). The carrier (1) contains a matrix of dot capacitors (9) formed between laminated layers (2) of ceramic material. In some cases, conductive layers are provided on the upper and lower surfaces of a thin film of ceramic material in which dielectric bodies are interspersed in an array of openings therein. The resultant ceramic dielectric combination has a coefficient of thermal expansion which matches the coefficient of thermal expansion of the silicon chip and the substrate thereby relieving stress upon the solder ball joints between the interposer and both the chip and the substrate. This minimizes the mechanical stress upon the solder ball joints during thermal cycling of the structure. Alternatively, an array of multilayer ceramic capacitors has an array of dielectric bodies located within holes in ceramic layers between capacitor plates, or entire arrays of capacitors are formed in the space between ceramic sheets. <??>In addition to its principal application in a chip carrier, other applications are in chip interposers and discrete capacitors for mounting on chip carriers.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a support or carrier for an integrated circuit chip, and in particular to a carrier having high capacitance in said carrier or between said carriers or in other structures carried on said carrier. Concerning carriers for chips.

As a conventional example, IBM Chikunical Disclosure Bulletin (hereinafter referred to as IBM TDB) No. 20
Volume, No. 9, pages 3436-3437 (February 1978 issue)
ROLusssow's “Internal
Capacitors and Resistors for Multilayer
A small article titled ``Ceramic Modules (Internal Capacitance and Internal Resistance for Multilayer Ceramic Modules)'' states:
A capacitor is installed in a structure in which a wiring layer or metallurgy is positioned between a pair of green sheets so as to be in contact with a through conductor or via, and both sides are coated with ceramic cylinders. An integrated multilayer ceramic package or module is disclosed. Instead, the via holes in a single green sheet are filled with dielectric paste to form a capacitor (FIG. 4 thereof).

“Multilayer
A small text entitled ``Ceramic Sandwiches'' describes the stacking of multiple layers and glasses, including layers with high and low dielectric constants k, and the structure (shown in Figure 2). An insert inserted therein to change the value of k without any electrode connection to the structure is disclosed.
This shows that the "multilayer ceramic" (MLC) molds that can be produced in this way are widely available.

U.S. Pat. No. 3,813,773 discloses stamping holes in a sheet of metal and filling these holes with an insulating material. This insulating layer provides electrical isolation rather than capacitance.

IBM TDB Vol. 15 No. 6, pages 1977 to 1980, Mr. CM McIntosh and AF Schmeckenbecher
"Packaging of Integrated Circuits" by Mr.
(Integrated Circuit Implementation)'' discloses positioning capacitors in a stack of preformed insulating sheets with vertical interconnects provided by metal vias. A single isolation capacitor is disclosed, but its capacity is limited. The insulating sheet is rigid and is not manufactured from ceramic green sheet. There is a space between the insulation sheets.

U.S. Patent No. 3,267,342 (inventors Pratt et al.
"Electrical Capacitor" refers to a capacitor in which a crystallized glassy substance is fused to a substrate. A metal capacitor plate made of finely divided metal is used with the glassy material. Another insulating layer of partially crystallized glass is fused to the capacitor plate. A portion of the plate extends beyond the insulating layer.
The expansion rate of this buffer layer may be comparable to that of the insulating layer. Includes extra capacitor plates and extra buffer layers.

Mr. McIntosh and IBM TDB Vol. 17, No. 3, pp. 862-863 (August 1974 issue)
"Low Dielectric" by Mr. Schmeckenbecher
Constant Pockets in Multilayer Ceramic
The article titled ``Low-k Pockets in Multilayer Ceramic Modules'' discloses the formation of low-k regions in the structure of stacked green sheets. A metallic paste and a filler paste are applied to place a plurality of low dielectric constant pockets around the sandwiched conductor within the ceramic module.

“Stress” by Mr. Brownlow, IBM TDB Vol.
Avoidance in Cofired Two Material
The article titled ``Ceramics'' discloses a sandwich-like capacitor structure between two plastic ceramic layers and a resin ceramic layer. The capacitor is located in the hollow space because it introduces into the green substrate volatile materials that are lost during firing of the ceramic material.

“Thick Film” in U.S. Patent Application No. 106640
Capacitor Having Very Low Internal
Inductance (thick film capacitors with very low internal resistance) are obtained by decoupling low inductance capacitors obtained by stacking very closely spaced ceramic sheets with metal plates, and Alternate pairs of plates are coupled to alternate electrodes. It is disclosed to couple opposite ends of the plates to respective electrodes such that current flows in opposite directions through adjacent facing plates.

It is an object of the present invention to minimize stresses resulting from thermal expansion mismatch between the material of the ceramic chip carrier or interposer structure and the highly insulating material, so that the thermal expansion coefficient of the entire structure is low yet well matched. In addition, it is an object of the present invention to provide a structure of a ceramic chip carrier or interposer provided with a built-in capacitor having a large capacitance value.

Another object of the invention is to provide a minimally stressed monolithic structure containing a large number of capacitors, preferably individually connected in parallel with each other, having a high capacitance value and minimal inductance.

Another object of the present invention is to provide a ceramic capacitor structure with minimum stress, minimum inductance, and maximum capacitance.

FIG. 1 is a sectional view of a multilayer ceramic chip carrier 1 carrying a chip 11. FIG. Chip 11
is supported by a C-4 solder ball bonded to a conductor pad 15. The pad 15 is connected to the conductor via 4.
5. The vias 45 are carried on conductor straps 44 extending perpendicular to the page for coupling to other vias. The obi 44 is
Coupled to respective vias 5, 6, 7 and 8. This includes bands 41, 42 and 4 that run perpendicular to the page to create interconnections between vias and pins 17.
It extends downward to 3. Other vias 4 and 5 are connected to pin 17 from strip 44 or other metal wire.
The pad 3 extends directly to the pad 3. A pin 17 is soldered onto the pad 3. Its basic structure, i.e. the carrier 1, is a laminated composition of ceramic sheets 2, in which metal conductors and capacitors 9 are included, with short connections of low resistance to the chip carrier with maximum capacitance and minimum inductance. Give the line and. The stacked layers of the array of capacitors 9 are optionally connected with vias 5, 6, 7 and 8 as shown briefly in FIG. Since the capacitor is very small and occupies only a small volume of the overall carrier, it does not adversely affect the overall thermal expansion characteristics of the carrier. Furthermore, since there are so many capacitors in the carrier, the overall value of the capacitors is large. This will be discussed in more detail below in connection with FIGS. 1 and 2. On the top surface of the carrier 1, several pads 15 (not shown) are connected to the signal lines X and Y.
is coupled to the fan-shaped metallurgy 40 in a conventional manner. The X and Y thin film wiring layers are
It is in layer 46 just below the top surface of carrier 1.

In FIG. 2, an intermediate interconnect substrate structure 10 is shown carrying a silicon chip 11 of a "large scale integrated" (LSI) circuit. The intermediate connection structure 10
is carried on a ceramic substrate 12. A solder ball joint 14 (known as a C-4 joint) is used to join chip 11 to intermediate connection structure 10. Solder ball joint 18 couples the intermediate connection structure to substrate 12 in a conventional manner. Solder ball joint 14 of chip 11 fits into pad 15 on intermediate connection 10. Joint 18 rests on contact 16 on substrate 12. On the underside of the board 12 pins 17 are adapted to be inserted into receptacles on a possibly larger circuit board (not shown).

The intermediate connection structure 10 has (a) the function of structurally supporting the chip 11 mounted by the joint 14, and (b) the function of providing a per-chip capacity of approximately 20 nf (10 ^-9 farads) per chip. There is a request to do so. Similar requirements exist for the carrier 1 shown in FIG.

In order to satisfy requirement (a), the structure of the intermediate connection structure or chip carrier must have a relatively low coefficient of thermal expansion α close to the coefficient of thermal expansion of the silicon material in which the chip 11 is incorporated. Preferably, the value of the coefficient of thermal expansion of the intermediate connection structure 10 or the carrier 1 lies between that of silicon and that of the substrate 12. Note that the substrate 12 is basically made of materials such as alumina and silica. If it is composed of alumina and silicon, the α of silicon is of the order of 3×10 ⁻⁶ per degree Celsius, and the α of the substrate 12 is of the order of 6×10 ⁻⁶ per degree Celsius.

In order to meet the requirements of (b), that is, carrier 1
Alternatively, in order to provide the required capacitance to the geometry of the intermediate connection structure 10, a high "permittivity" (ε _r )
is necessary. Materials with high ε _r such as barium or strontium titanate have a
It has an α value of 10×10 ^-6 .

There is a dilemma because a substance that satisfies requirement (a) does not satisfy requirement (b). I tried to mix particles of a substance with high ε _r and high α with particles of a substance with low _ε r and low α, but it did not work. When a substance with low ε _r and low α is added to a substance with high ε _r and high α,
Composite mixed materials (carrier 1
Alternatively, it is faster for ε _r of the intermediate connection structure 10) to decrease (see FIG. 3). The reason why _{ε r} of the composite material decreases faster is clear from a model in which a capacitor C _Hi with a high ε _r is coupled in series with a capacitor C _Lp with a low ε r.

For example, 1/C _nix =1/C _Hi +1/C _LpThe effective capacitance C _nix is mainly determined by the capacitor with low ε _r . For example, C _Hi =1000 and C _Lp =10
Then, C _nix =9.90. This is very close to 10, but slightly less than that value. In other words,
Substances with low ε _r in a matrix have a strong influence on the effective value ε _r of the matrix. A thin metal layer (on the order of micrometers or thinner) made of a metal material with high ε _r on a substrate with a low coefficient of thermal expansion.
Other attempts to fabricate capacitors by attaching them were unreliable due to cracks and pin-like holes.

According to the invention, the carrier 1 or solder ball joint 14 connected to the C-4 joint
and 18, the primary structure of which carries a material with low ε _r and low α, but also has the required capacitance values. This is achieved by producing a high ε _r material in parallel with a low ε _r material in a single layer.

In FIG. 4, ceramic sheets 128, 12
0, 127 and 131 deposits are shown. This figure shows that the space between sheets 127 and 131 may contain multiple layers beyond those shown. A number of layers similar to layers 120 and 127 are alternately placed in the arrangement to form sheets 128 and 131.
forming a capacitor between them. Layers 120 and 1
A hole was punched in the green sheet from which the sheet 27 was formed (see sheet 20 in FIG. 8). Metal paste in several holes 121a is deposited to form vias 129, 130 and 133 and connection contacts 129', 130' and 133'.
When multiple sheets are assembled, sheet 12
Contacts are formed to provide electrical connections to the capacitors formed at 0 and 120, and through vias are formed. A high dielectric constant material 122 is deposited in the remaining holes 121 arranged in a predetermined pattern, and conductive layers 124, 125 are deposited.
and 132, forming a sandwich shape between each other. This forms a capacitor in an array that extends perpendicular to the plane of the paper, extends to the left and right for the required length, and extends downward to the required depth over several layers. Ru. Examples of the values of bias voltages that can be applied to the various terminals of a capacitor formed in a stack of ceramic sheets include negative V ₁ , positive V ₂ and negative V ₃ voltage contacts 129',
133' and 130' are shown. Illustrated on the top surface of layer 127 is conductor 125, which connects via 129 to dielectric material 122 in hole 121.
and to a capacitor element formed by conductors 125, 124 and 132. Similarly, conductor 125' also couples to another dielectric element 122 adjacent to via 130. Conductors 125 and 125'
is in an interpolative positional relationship with the conductors 124 and 132.

FIG. 5 is a cutaway view of a capacitor array that is a modified version of the capacitor array shown in FIG. Hole 2 in the green sheets 228, 220, 227 and 231
21a is via 229, 229a, 233, 23
All filled with metal for 0 and 230a. A high dielectric constant material 222 connects conductor 224 (coupled to via 233 and flat portion 233') and flat portions 229' and 23 of vias 229a and 230a.
0'. Vias 229a and 230a are coupled to vias 229 and 230 by conductors 225 and 225'. in this case,
A capacitor is formed between layers 220 and 228 of ceramic material. The area shown in FIG. 5 is also only a portion of the overall structure that is to be used as a chip carrier or intermediate connection structure. Its width and depth perpendicular to the paper would be large, and layers 228, 220, and 227 could be repeated as many times as necessary to provide the required capacity. In practice, the capacitor is formed by the upper three layers shown in FIG.

Figure 6.1 is a perspective view of one capacitive element in an array of elements in a configuration of the present invention in which capacitive elements are formed between ceramic layers. A dielectric layer 322 is sandwiched between two metal layers 324' and 325 in a sandwich pattern, as shown in detail in FIG. 6.2. The metal layers 324' and 325, which serve as electrodes, are also in the sixth.
As shown in Figure 2, conductive vias 330 and 3
33.

In Figure 6.2, several ceramic layers 32 are shown.
8, 320, 327 and 331, the number of pairs of these layers 320 and 327 is as many as will provide the required capacitance. Vias 329, 333 and 330 are connected to pads 329', 333' and 330'.
is arranged similarly to the one above with . layer 320
On the lower surface of the
4' and the dielectric layer 322 below each
I'm holding it in between. A dielectric layer 322 is positioned on a layer of metal 325 that forms another electrode plate of the two capacitors shown. Layer of metal 325 is coupled to via 333 by one of a plurality of contacts 333'. In this embodiment, all capacitor material between the ceramic layers is formed over the ceramic layers by a silk screen mask. That is, metal layers 324, 324', metal layer 325, and dielectric layer 322 on ceramic substrate 320 are formed on the top surface of ceramic substrate 327.

Figure 7.1 shows that ceramic capacitors are formed between the ceramic layers in the ceramic carrier of Figure 1 having an array of capacitors in the manner of Figures 4, 5 and 6.2. , and modified so that empty or partially filled spaces are formed above and below each capacitor. As in FIG. 6.2, there is a sandwich-like structure consisting of a conductor 424, a dielectric layer 422 and an underlying conductor 425. Above and below this conductor, in its assembled and fired carrier structure,
As shown in FIG. 7.2, there is a volatile or partially volatile paste 450 that becomes a void 460.
Preferably, layers 428, 420, 427 and 431 are ceramic layers.

Manufacturing Method Intermediate connection structure 10 of FIG. 2 is manufactured by "multilayer ceramic" (MLC) techniques. 8-11 show structures very similar to the structure of FIG. The method of attaching signal lines, etc. by interconnection is described below in connection with FIGS. 8-11.

(A) First, please refer to Figures 8 and 9. In the first stage of manufacturing the intermediate connection structure 10 (FIG. 2), a green sheet of soft, pliable material with a thickness of approximately 0.10 mm is prepared.
Holes 21 and 21a are bored in the ceramic sheet 20. For example, an array of 30 x 30 holes with a diameter of 0.15 mm are drilled with a center spacing of 0.25 mm. Hole 21a
are metal electrode vias 29 and 30 (9th
They are separated from each other so as to provide electrical contact via (Fig.). The holes 21 are filled with dielectric paste to form a dielectric cylinder 22 made of a high _{ε r} material as shown in FIG. A screening process is used to squeeze out the dielectric paste into the holes 21 of the green sheet 20 to form the cylinders 22 through the holes of the mask. The dielectric paste is then dried. The hole 21a is protected by a mask and left empty during this time.

(B) Next, in FIG. 9, another screening operation deposits metal fill paste to form a blanket-like metal capacitor plate (electrode) 24. Incidentally, in the hole 21 under this plate 24, a substance with a high ε _r that forms the aforementioned columnar body 22 is adhered. This screening process also fills holes 21a in the pattern shown with vias 29 and 30 of metal fill paste, providing contact 29' above via 29. This same process is the first
The hole 21a in the layer 27 in Figure 0 is also made in the opposite direction from left to right.

(C) In FIG. 10, a capacitor structure is manufactured by stacking at least some of the sheets 28 (top), 20 and 27 and 31 (bottom). Several different sets of sheets 20 and 2
7 may be included in the structure to increase the capacity shown. The top sheet 28 consists of a ceramic sheet having electrical vias 29 and 30 for providing electrical contacts or electrodes. However, the sheet 28 does not include the dielectric cylinder 22. Several high ε _r filler sheets 20 are included in the structure, as shown in FIG. Furthermore, sheets 27, which are mirror images of sheet 20, are stacked alternately with said sheet 20. A metal plate 24 on sheet 20 is coupled to electrodes 30' and vias 30 above and below, respectively. Metal capacitor plates 25 are coupled above and below vias 29, which are coupled to electrode contacts 29'.

Electrodes 29' and vias 29 and electrodes 30' and vias 30 extend from sheet to sheet in their respective locations to collectively form one via or overall vias 29 and 30, with the internal vias Electrode contacts 29' and 3
0' by providing a large enough surface to correct the misalignment with other vias.

A bottom sheet 31 is shielded with a metal layer 32 to form a bottom capacitor plate, which is connected to vias 3.
Connected to 0 above and below. Via 30 is seat 3
1 is coupled to an electrode contact 30' on the lower surface of 1. At the left end of the via 29, a pair of electrode contacts 29' are provided one above the other. The sheet 31 does not include the dielectric cylinder 22.

Pressure and heat are applied to the stack of green sheets 28, 20, 27 and 31. The result is one combined structure in which the set of metal plates 24, 25 and 32 and the cylindrical body 22 form a capacitor. Via 29 is, for example, a positive electrode and via 30 is a negative electrode. Several external electrode contacts 29' and 30'
Contact point 15 in FIG. 1 that supports silicon chip 11
If necessary, it is bonded to a C-4 solder ball as shown in FIG. Increase the number of layers similar to layers 20 and 27 until as many n pairs of layers (where n is a positive integer) as necessary to provide the desired capacitance value have been assembled as shown in FIG. This allows the capacity to be increased as required.

(D) The composite structure is then sintered in an appropriate external environment that is compatible with both high ε _r materials and metals and low ε _r materials and metals.

Examples of suitable systems of materials that can be sintered together in air are as follows.

Low ε _r - Glassy ceramic (MgO
−Al ₂ O ₃ −SiO ₂ −TiO ₂ ) or alkaline earth porcelain (Al ₂ O ₃ −SiO ₂ −CaO−Na ₂ O−K ₂ O) High ε _r − BaTiO ₃ Metals − Pd/Au This composite Sintering the structure provides high capacity. This is because the distance between the metal plates (2 in Figure 10)
4 and 25 and between 25 and 32), a controllable amount of a substance with a high ε _r can be applied in parallel to a substance with a low ε _r . The α of the substrate 12 material is kept low. This is because the support structure (ie, the bonded matrix) is of low α.

Calculation of the capacity of intermediate connection structures Examples of typical numerical values are shown below.

Sheet thickness = 0.075 mm Via hole diameter = 0.15 mm ε _α of material with high r = 10 × 10 ^-6 /℃ ε _r of material with high ε _r = 5000 α of material with low ε _r = 4 × 10 ^-6 /°C The pore capacity of a 30x30 matrix is approximately 10nf per layer. To successfully use this technique, it is necessary to prevent air and low ε _r gaps from entering the metal-ceramic interface. This problem usually does not occur if there is good metal-to-ceramic adhesion. This is because metal is relatively easy to stretch and can accommodate small strains (less than 1 μm).

In addition to solving the problem of low α and high ε _r , several other advantages of this design are listed below.

(1) Chip carrier 1 or intermediate connection structure 1
In the embodiment of a capacitor in 0, conductive vias can be interspersed within the capacitor structure and isolated from the capacitor's electrode plates. The fan-shaped pattern for the signal line is also normal Cr.
-Cu-Cr surface wiring layer allows for attachment to the top of the intermediate interconnect structure.

(2) This capacitor structure described above can be manufactured in a large substrate (1 in FIG. 1 or 12 in FIG. 2), thereby allowing the intermediate connection structure 10
and its associated problems. Such an embodiment solves the problem of being fired together as mentioned in (1), and
It is particularly useful when Cu is used for signal lines.

(3) The capacitor structure described above can be used as a separate capacitor disposed along the sides of the chip at the top of the package. Such capacitors are shown in FIGS. 12 to 14 below.
Electrical contacts due to the arrangement of the areas allow low inductance connections to be made.

(4) For thin film implementations (Cu/polyimide signal lines on the surface of the board), the capacitor structure described above is an alternative technique for integrating the capacitor within the board (see my US Patent Application No. 164,119). .

(5) This technique is also applicable to the general field of ceramic capacitors where the coefficient of thermal expansion is different from that of materials with high ε _r . Such a situation exists if the rate of expansion of the capacitor is optimized for the structure attached to the next level of one package structure.

FIG. 12 shows a multilayer ceramic capacitor 70 using a matrix of holes into which a high dielectric constant material is added to obtain high capacitance. This layer of metal, which acts as an electrode, is deposited over the interface between the layers of ceramic material when the capacitor is assembled. Solder balls 96, 97, 98 and 9
9 is illustrated as an array of C-4 solder balls used to bond to the chip carrier. The capacitor 70 is adapted to be positioned on a chip carrier such as the carrier 12 of FIG. 2 or even on the intermediate connection structure 10. FIG. 13 shows a cross-sectional view of the capacitor of FIG. 12 along line 13--13. Solder balls 96, 97, 98 and 99 are shown at the root of the capacitor. ball 9
6 is coupled to an electrode 90 illustrated with a - symbol representing negative polarity. + represents positive polarity
A pair of capacitor plates 91 and 92 are coupled to solder balls 97, which are illustrated by symbols. These plates are attached to both surfaces of ceramic layer 83. Plates 91 and 92 are thus coupled to the same polarity. Let's step aside and explain each layer in Figure 13. layers 80, 81 of ceramic material (carrying plate 90), (perforated and containing cylinders 22 of dielectric material);
There is a layer 82, then a plate 91, then a ceramic layer 83, next to which a plate 92,
Ceramic layer 84 (perforated and containing dielectric cylinder 22), Negative plate layer 93 (bonded to negative solder ball 98), Ceramic layer 85 (bonded to solder ball 98). )
A layer of plates 94 follows. Next ceramic layer 86
is a cylindrical body 22 of dielectric material with holes drilled therein.
between plates 94 and 95. Plate 95 is coupled to positive solder ball 99.
The next ceramic layer is layer 87 laminated to plate 95 and the last ceramic layer is layer 88. At the lower ends of the plates 90 to 95, as shown in FIG. 14, there are tabs 101 as an overhang of the plate 90, and tabs 102, 103, and 104 as the overhangs of the plates 91, 92, and 93, respectively. . It can be seen in FIG. 13 that plates 91 and 92 are joined by a semicircular body 100 bridging the space between tabs 102 and 103. Several more semicircular bodies 100 are shown in FIG. 13: one for coupling plate 90 to solder ball 96, one for coupling plates 93 and 94 to solder ball 98, and one for coupling plate 95, which is an electrode. This is for connecting the solder ball 99 to the solder ball 99.

As a modification of Fig. 13, “A Multi
Layer, Ceramic Carrier for High
Switching Speed VLSI Chips
"Multilayer ceramic carrier for VLSI chips)"
As shown in FIG. 3 of the aforementioned U.S. patent application entitled ``Semi-circular body 1'' is used to connect the capacitor plates to each other when the tabs extend alternately from several sets of capacitor plates.
00 may span them.

In Figure 14, the position of the solder ball is oval 1.
10, 111 and 112, this only indicates how close solder balls 96, 97 and 98 are located. For each capacitor plate 90, 91, etc.,
Semicircular body 100 and solder ball 9 of FIG.
Tabs 101, 102 connected to 6 to 99
Please note that there are several such things. 14th
The figures clearly illustrate aspects of the individual layers 81, 90, 82, etc., which are similar in many respects to the layers of FIGS. 8, 9, and 10.

The potential of electrode 97 increases and plates 90 and 91
When the capacitor consisting of
and 92 in parallel, and the currents applied to the dielectric layers 82 and 84 of that capacitor are in opposite directions. When the currents flow in opposite directions, the resulting electric fields cancel each other out, reducing inductive coupling.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a chip carrier including an array of capacitors according to the present invention. FIG. 2 is a side view of a chip carrier carrying a VLSI semiconductor chip equipped with a pair of intermediate connection structures. Figure 3 shows the dielectric constant ε and thermal expansion as a function of the percentage composition of a material having two opposing variables with a high dielectric constant and a high coefficient of thermal expansion at one end and a low dielectric constant and a low coefficient of thermal expansion at the other end. FIG. 3 is a graph showing normalized values of the rate α; FIG. 4 is a sectional view showing the structure of the chip carrier according to the present invention before being laminated,
The laminated structure includes a plurality of ceramic sheets stacked on top of each other, and the vias and connectors that cooperate with the ceramic sheets are made of metal and high-permittivity cylindrical bodies located in the plurality of holes in each ceramic sheet. FIG. 3 is a diagram illustrating a chip carrier structure providing a multi-level capacitor array. Fifth
The figure is a sectional view showing a modification of the chip carrier structure shown in Figure 4, in which an opening in a ceramic sheet is formed so that a capacitor is formed by covering the tip with a cylindrical body having a high dielectric constant and providing an electrode on the other surface. Alternatively, it is a sectional view showing a capacitor having the present structure in which the hole includes a metal cylindrical body. Figure 6.1 shows that a capacitor is formed by laminating a metal layer and an insulating layer that acts as a dielectric between ceramic green sheets before firing to form the array of capacitor elements in this structure. However, this is a third modification of the capacitor laminate based on the concept of FIG. 1, and is a perspective view that can be applied by modifying the structure of FIGS. 4 and 5. FIG. 6.2 is a cutaway sectional view similar to FIGS. 4 and 5 of a capacitor structure using the capacitor according to FIG. 6.1. Figure 7.1 shows a capacitor in a chip carrier segment where the capacitor is formed between the green sheets with volatile or partially volatile paste layers filled with inert particles on the top and bottom. FIG. 6.2 is a view similar to FIGS. 4, 5 and 6.2, showing the arrangement as a green, non-laminated variant. Figure 7.2 shows a green sheet of ceramic material after firing with voids or partially filled voids provided above and below the capacitor to drive out volatile parts of the paste during firing.
1 is a diagram showing the structure of FIG. FIG. 8 is a cross-sectional perspective view of a perforated sheet for use on a chip carrier or intermediate connection structure in which cylindrical bodies of high dielectric constant material have been inserted into several perforations or holes. Figure 9 shows the top surface of the sheet after processing to include a wiring layer applied where needed in the form of a metal-filled paste covering the sections where the capacitor plates need to be located and filling the remaining holes. FIG. 9 is a diagram showing the structure of FIG. 8; FIG. 10 is a cutaway view of the structure of FIGS. 8 and 9 in which a number of ceramic sheets are perforated in various patterns in a predetermined pattern to form a multilayer ceramic capacitor; FIG. .
FIG. 11 is an elevational view of the structure of FIG. 1st
FIG. 2 shows a vertically oriented multilayer ceramic capacitor structure according to the present invention. FIG. 13 is a cross-sectional view taken along the line 13--13 in FIG. 12. FIG. 14 is a cutaway view of the vertical capacitor of FIGS. 12 and 13. FIG. 1...Carrier, 2...Ceramic sheet, 3
... Contact, 4 to 8 ... Via, 9 ... Capacitor, 11 ... Chip, 12 ... Ceramic substrate,
17...Pin (terminal).

Claims (1)

[Scope of Claims] 1. A carrier supporting a circuit chip on one surface, and electrically connecting the chip through the carrier to an external connection terminal on a surface opposite to the one surface of the carrier. a plurality of laminated ceramic sheets having a plurality of through conductors connected to the through conductors; and dots located between at least one pair of the laminated ceramic sheets and separated from the through conductors. A plurality of small capacitor elements positioned as above, and two layers of conductive material sandwiching a layer of high dielectric constant material constituting the capacitor element, one of which is used as one through conductor, and the other is used as another through conductor. and a layer of conductive material electrically connected to the conductor.