JPS6348355B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field to which the invention pertains] The present invention relates to a display device that displays characters, graphics, etc. on a display screen. For more details,
The present invention includes a display means such as a cathode ray tube (abbreviated as CRT), and an image memory having a bit array that corresponds two-dimensionally to the pixel array of the display screen. This invention relates to a display device in which a rectangular bit array of M×N bits obtained by dividing the image memory into a lattice is used as an access unit of an image memory.

[Description of prior art]

FIG. 1 is a block diagram showing an example of a conventional display device of this type. This device includes a control device (hereinafter abbreviated as CONT) 1, a memory module (hereinafter abbreviated as MM) 2 that is controlled by this CONT 1 and constitutes an image memory, and a memory module (hereinafter abbreviated as MM) 2.
A display control device (hereinafter abbreviated as DC) 3 which inputs the signal read out from the MM2, and a cathode ray tube (hereinafter abbreviated as CRT) 4 which displays the display data read out through the DC3 in a raster scan method. It consists of

FIG. 2 is a block diagram showing the detailed configuration of MM2. The MM2 includes a memory section 5 that stores image information to be displayed on the CRT4, and an address bus.
A memory address register (hereinafter referred to as
(abbreviated as MAR) 6, a memory buffer memory (hereinafter abbreviated as MBR) 7 that temporarily holds data (image information) applied via a data bus DATA, and a control bus RWCB,
It is configured to include a read/write control circuit (hereinafter abbreviated as RWC) 8 that controls reading and writing of the memory section 5.

In FIGS. 1 and 2, the memory unit 5 corresponds two-dimensionally to a pixel array in which the number of pixels in the horizontal scanning direction is N×S pixels and the number of pixels in the vertical direction is M×R pixels on the display screen. The memory has a bit array structure, and is capable of storing one bit of information in each storage location corresponding to each pixel.

FIG. 3 shows that the two-dimensional bit array of the memory section 5 is R.
FIG. 2 is a schematic diagram showing how the bit array is divided into R×S rectangular bit arrays arranged in rows and S columns in a lattice pattern. One rectangular bit array is an array of N bits in the horizontal direction and M bits in the vertical direction. Hereinafter, the rectangular bit array described above will be referred to as a block (abbreviated as BLK). Also, the third
In the figure, (i, j) (i=0,1...,R-
1, j = 0, 1, ..., S-1) is an address indicating the position of BLK in the memory section 5 divided into a grid, and BLK (i, j) is the address of the i-th BLK in the memory section 5. It means the BLK located in the jth column of the row.

Here, CONT1 connects MM2 via each bus.
It controls data writing and data reading for CONT1 and MM2, and data exchange between CONT1 and MM2 is performed in units of blocks. accordingly
MBR7 holds one block of data M×N bits.

In addition, in FIG. 3, four integers i, j,
h, l (0≦i, h≦R-1; 0≦j, l≦S-
When the following equations (1) to (3) hold simultaneously during 1),
BLK (i, j) and BLK (h, l) are said to be connected.

|h-i|=0 or 1 ...(1) |l-j|=0 or 1 ...(2) |h-i|+|l-j|=1 or 2 ...(3) CONT1 When writing data to MM2,
First, CONT1 obtains the address (i, j) of BLK where new data should be written to change the display screen and the M×N bit change data to be written to that block, and sends it to the bus ADDR.
Through the bus DATA, (i, j) is set to MAR6, and M×N bit change data is set to MBR7 through the bus DATA. Next, CONT1 is the bus RWCB
Issue a write request to RWC8 through
Write the contents of MBR7 to BLK(i,j) of memory unit 5.

FIG. 4 is an explanatory diagram showing the relationship between the straight line L written in the image memory where R=4 and S=4 and each BLK constituting the image memory. In Figure 4, BLK2, 0,
BLK1, 1, BLK1, 2 and BLK0, 3 each contain pattern data of straight line L.
CONH1 is a write pattern including partial pattern data of straight line L to be written to each BLK.
Data is generated sequentially using a specific algorithm, and each time data generation for one BLK is completed, it is transferred to the MM2 according to the write operation described above.
write to. In general, generation of pattern data using the specific algorithm described above can be completed in a shorter time than the time required to write to MM2 (write cycle time) by realizing the execution of the algorithm using wired logic. is possible.

Figure 5 shows the pattern of straight line L in Figure 4.
This is a timing chart showing the procedure for writing data to image memory.

In Figure 5A, the period G0 is BLK2,0
This is the period during which CONT1 generates the pattern data to be written to the
This is the period required for writing to BLK2 and BLK0.
Below, in C, H, G, periods G1, G2, G
3 are BLK1, 1, BLK1, 2, BLK respectively
The pattern data to be written to 0,3
The periods T1, T2, and T3 are the periods in which CONT1 is generated.
This is the period required to write pattern data to BLK1, BLK1, BLK2, and BLK0, BLK3.

First, in period G0, CONT1 is BLK2,
It generates write pattern data to 0, and starts writing the same data to BLK2 and 0 at the same time as the generation is completed. This writing is performed during period T0. At the same time as this writing starts,
CONT1 is the write pattern to BLK1,1.
Start generating data. This generation is performed during period G1. Here, writing of the pattern data generated in the period G1 to BLK1, 1 cannot be started until the period T0 ends. CONT1 is the period T0 from the end of period G1
You will have to wait until the end of the process. Thereafter, at the same time as the period T0 ends, CONT1 starts the period T1 and the period G2. Below are these operations.
By repeating until the writing to BLK0 and BLK3 is completed, the straight line L to the image memory is
Writing of pattern data is completed.

In this way, in conventional devices, multiple image memories are used to display characters, figures, etc.
When writing pattern data to BLKs continuously, no matter how fast the pattern data to be written to each BLK is generated, writing to a certain BLK starts immediately before. There is always a wait until the end of the write cycle to other blocks. For this reason, the conventional device has the disadvantage that it cannot perform high-speed display commensurate with the high-speed generation of pattern data to be written into each block. Similar drawbacks also occurred when reading from image memory.

[Object of the present invention]

An object of the present invention is to eliminate such drawbacks of conventional devices and to realize a display device that can display characters, graphics, etc. at high speed by effectively utilizing the general characteristics regarding access to image memory. This is what I am trying to do.

[Summary of the invention]

The device according to the present invention configures the image memory with four memory modules that can each be accessed independently, and can store any two connected BLKs in the image memory in different memory modules. It is characterized by having an address conversion mechanism like this.

[Configuration of the present invention]

FIG. 6 is a block diagram showing an example of the apparatus according to the present invention. In the figure, 2a, 2b, 2
c and 2d are four memory modules (hereinafter referred to as each) constituting one image memory 2.
(abbreviated as MM ₀ , MM ₁ , MM ₂ , MM ₃ ), and the detailed structure of each is the same as that in FIG. 2. 9 is the ADRC conversion mechanism (hereinafter abbreviated as ADRC), and CONT
1 and is connected via bus ADDR. MM ₀ ,
MM ₁ , MM ₂ , and MM ₃ are all connected to CONT1 via bus DATA and bus RWCB,
ADRC9 also refers to the address bus (MADR).
and are connected via the signal line MSEL. Here, the signal line MSEL transmits information for selecting one of MM ₀ 2a to MM ₃ 2d from ADRC9, and the bus MADR transmits information for selecting one of MM 0 2a to MM 3 2d, and the bus MADR transmits information for selecting one of MM 0 2a to MM 3 2d.・In the module
BLK position information is transmitted from ADRC9.

The access unit for each MM ₀ 2a to MM ₃ 2d is
BLK and any location in image memory
BLK, BLK (i, j) (i=0,1...,R-
1; j=0,1...,S-1) is the following equation (4), (5)
It is stored at address g in memory module MMp determined by the formula.

p=(2i+j)4...(4) g=(i/2)・{(S+1)/2}+j/2
...(5) However, "/" and "/" represent the quotient and remainder of an integer, respectively.

According to equation (4), each BLK in the image memory
You can create any two concatenated objects in image memory by allocating a memory module to
BLK will always be stored in different memory modules.

ADRC9 transfers the BLK address (i, j) in image memory 2 from CONT1 to the bus.
received through ADDR, calculates p and g according to equations (4) and (5), and as a result, BLK(i,
j) is stored in the memory module MMp
Sends information for selecting BLK(i,j) onto the signal line MSEL, and sends the address g of BLK(i,j) in MMp onto the bus MADR.

FIG. 7 is a diagram showing the values of p and g of each BLK in an image memory where R=4 and S=4, as a specific example of calculation of equations (4) and (5). be.

[Operation of the present invention] The operation of the device configured as described above will be explained using the case where the pattern data of the straight line L shown in FIG. 4 is written into the image memory as an example. This will be explained with reference to the chart.

In Figure 8 A, C, H, G, periods G4, G
5, G6, G7, CONT1 is BLK2,0,
This is a period for generating pattern data to be written to BLK1, 1, BLK1, 2, and BLK0, 3, respectively. In FIG.
2,0,BLK1,1,BLK1,2,BLK0,3
This is the period required to write pattern data to.

First, in period G4, CONH1 is BLK2,
Generates pattern data to be written to 0 and sends it to the bus DATA. at the same time
CONT1 is connected to ADRC9 through bus ADDR.
Send BLK addresses 2 and 0. ADRC9 is
p=0 and g=2 are calculated according to the above equations (4) and (5), information for selecting MM ₀ 2a is sent to the signal line MSEL, and address g of MM ₀ 2a is sent to the bus MADR. =2 is sent. After that, CONT1 is the bus
By issuing a write request to MM ₀ 2a through RWCB, the write cycle T of BLK2,0 is
4 is started.

CONT1 starts BLK at the same time as the start of period T4.
Generation of pattern data to be written to MM 3 2d (period G5) is started, and after the generation is completed, writing to address g=0 of MM ₃ 2d is started using the same procedure as above. At this time, MM ₃ 2d is
Since it is possible to access independently of MM ₀ 2a, there is no need to wait for the end of the write cycle of BLK2,0 when writing pattern data to BLK1,1.

Next, at the same time as the start of the write cycle T5 to BLK1,1, CONT1 is
Start generating pattern data for BLK1 and BLK2. After the generation is complete, follow the same steps as above.
Writing to address g=1 of MM ₀ 2a is started, but at this time it is necessary to wait for the end of period T4. However, this waiting time is shorter than the waiting time that always occurred in conventional devices.

These operations are repeated until writing of pattern data to BLK0 and BLK3 is completed.

[Effects of the present invention]

As explained above, according to the device according to the present invention, in continuous access to a plurality of connected blocks, the start of writing to a certain BLK does not need to wait for the end of the write cycle started immediately before, or Even when it is necessary to wait, the waiting time is shorter than before,
Display and manipulation of characters, graphics, etc. can be performed faster than with conventional devices. Note that these effects are also effective when pattern data is read out continuously from a plurality of connected BLKs.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing an example of a conventional display device, and FIG. 2 is a block diagram showing an example of a conventional display device.
Block diagram showing the detailed configuration of the module, Part 3
The figure is a schematic diagram showing an example of dividing the two-dimensional bit array of the image memory into a lattice pattern, Figure 4 is an explanatory diagram showing the state in which straight line pattern data is stored in a specific image memory, and Figure 5 The figure shows the fourth
6 is a block diagram showing an example of the device according to the present invention, and FIG. 7 is a timing chart of a conventional device when writing data to an image memory. FIG. 8 is a diagram showing memory module allocation for BLK and address allocation within each memory module, in the device of the present invention,
This is a timing chart when writing the straight line pattern data of FIG. 4 into the image memory. 1...Control device (CONT), 2...Memory module (MM), 3...Display control device (DC), 4...Display means (CRT), 5...Memory section, 6...Memory address register (MAR), 7...Memory buffer register (MBR), 8...Read/write control circuit (RWC), 9...Address conversion mechanism (ADRC).

Claims (1)

[Scope of Claims] 1. A rectangular bit array having a bit array structure two-dimensionally corresponding to a pixel array on a display screen, and obtained by equally dividing the two-dimensional bit array on a grid, and The image memory includes an image memory whose access unit is a rectangular bit array, the bits of which do not belong to any other rectangular bit array, and a control device that edits the contents of the image memory in units of the rectangular bit array. In the display device configured to display characters, figures, etc. on a display screen, the image memory is configured with four memory modules each of which can be accessed independently, and the control device and the image memory are connected to each other. Any two rectangular bit arrays that are in a concatenated positional relationship on the display screen between them are stored in different memory modules of the four memory modules, and this storage is performed in each of the rectangular bit arrays. All bits belonging to the memory are the same.
A display device characterized in that it is provided with an addressing device for storing it in a module.