JPS6349066B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a backup device for a control system for an internal combustion engine for an automobile, which prevents the idle speed from increasing abnormally even when the idle speed control system fails. As interest in environmental conservation by preventing air pollution and the depletion of energy resources increases, control devices are designed to comprehensively control the operating conditions of automobile gasoline engines to improve exhaust gas conditions and improve fuel efficiency. As a result, microcomputers are being used to collect signals from sensors that provide various data that represent the operating status of the engine, such as a cooling water temperature sensor and an _O2 sensor that provides the oxygen concentration in exhaust gas. The electronic engine control device (EEC) controls various factors such as fuel intake, fuel supply amount, ignition timing, exhaust gas recirculation amount, and idle speed to ensure that the engine is always in the optimal operating state. It has come to be used. An example of a system in which such EEC is applied to a fuel injection type internal combustion engine is shown in FIGS. 1 to 6. Fig. 1 is a partial cross-sectional view schematically showing the entire engine control system.
6 and is supplied to cylinder 08. The gas burned in the cylinder 08 passes through the exhaust pipe 10 from the cylinder 08 and is discharged into the atmosphere. The throttle chamber 04 is provided with an injector 12 for injecting fuel, and the fuel injected from the injector 12 is atomized within the air passage of the throttle chamber 04 and mixed with intake air. A mixture is formed, and this mixture is supplied to the combustion chamber of the cylinder 08 through the intake pipe 06 when the intake valve 20 is opened. A throttle valve 14 is located near the outlet of the injector 12.
16 are provided. The throttle valve 14 is configured to be mechanically interlocked with the accelerator pedal and is driven by the driver. On the other hand, the throttle valve 16 is arranged so as to be driven by the diaphragm 18, and is fully closed when the air flow rate is small.As the air flow rate increases, the negative pressure on the diaphragm 18 increases, so that the throttle valve 16 It begins to open and suppresses the increase in inhalation resistance. An air passage 22 is provided upstream of the throttle valves 14 and 16 of the throttle chamber 04, and this air passage 22 includes a thermal air flow meter consisting of an electric heating element,
That is, a flow rate sensor 24 is provided, and an electric signal AF that changes depending on the air flow rate determined from the relationship between the air flow rate and the amount of heat transferred from the heating element is taken out. Since the flow rate sensor 24 made of this heating element (hot wire) is installed in the bypass air passage 22, it is protected from high-temperature gas generated when the cylinder 08 backfires, and it is also protected from being contaminated by dust in the intake air. It is also protected from. The outlet of this bypass air passage 22 is opened near the narrowest part of the bench lily, and the inlet thereof is opened on the upstream side of the bench lily. Fuel supplied to the injector 12 is supplied from a fuel tank 30 to a fuel pressure regulator 38 via a fuel pump 32, a fuel damper 34, and a filter 36. On the other hand, pressurized fuel is supplied from the fuel pressure regulator 38 to the injector 12 via a pipe 40.
Fuel is returned from the fuel pressure regulator 38 to the fuel tank 30 via the return pipe 42 so that the difference between the pressure in the intake pipe 06 where fuel is injected from the fuel pressure regulator 38 and the fuel pressure to the injector 12 is always constant. It's summery. The air-fuel mixture taken in from the intake valve 20 is transferred to the piston 5.
0 and is combusted by a spark from the ignition plug 52, and this combustion is converted into kinetic energy. The cylinder 08 is cooled by cooling water 54, the temperature of this cooling water is measured by a water temperature sensor 56, and this measured value TW is used as the engine temperature. A high voltage is supplied to the spark plug 52 from an ignition coil 58 in accordance with the ignition timing. Further, the crankshaft (not shown) is provided with a crank angle sensor that outputs a reference angle signal and a position signal at every reference crank angle and every fixed angle (for example, 0.5 degrees) according to the rotation of the engine. The output of this crank angle sensor, the water temperature sensor 56
output signal TW and electrical signal from heating element 24
The AF is inputted to a control circuit 60 consisting of a microcomputer or the like and subjected to arithmetic processing, and the output of this control circuit 60 drives the injector 12 and the ignition coil 58. Furthermore, the throttle chamber 04 has a throttle valve 1.
A bypass 26 is provided that straddles the intake pipe 6 and communicates with the intake pipe 06, and this bypass 26 is provided with a bypass valve 61 that is controlled to open and close. This bypass valve 61 faces the bypass 26 provided by bypassing the throttle valve 16, and is controlled to open and close by a pulse current, and the cross-sectional area of the bypass 26 is changed depending on the amount of lift. The drive section is driven and controlled by the output of the control circuit 60. That is, the control circuit 60 generates an opening/closing periodic signal for controlling the driving section, and the driving section adjusts the lift amount of the bypass valve 61 based on this opening/closing periodic signal. Therefore, the injector 12 shown in FIG. 1 is controlled to control the air-fuel ratio (A/F) and fuel increase control, and the bypass valve 61 and the injector 12 control the engine speed at idle (ISC).
Do this. FIG. 2 shows an ignition system in which a pulsed current is supplied to a power transistor 64 through an amplifier 62, which turns the transistor 64 on. As a result, the ignition coil 58 from the battery 66
Primary coil current flows to. When the input pulse current falls, the transistor 64 is cut off, and
A high voltage is generated in the secondary coil of the ignition coil 58. This high voltage is distributed via the power distributor 70 to each of the spark plugs 52 in each cylinder of the engine in synchronization with the engine rotation. FIG. 3 is for explaining an exhaust gas recirculation (EGR) system, in which constant negative pressure from a negative pressure source 80 is applied to a control valve 86 via a pressure control valve 84.
The pressure control valve 84 controls the ratio of the negative pressure of the constant negative pressure source to the atmosphere 88 according to the ON duty ratio of the repeated pulses applied to the transistor 90, and controls the state of application of the negative pressure to the control valve 86.
Therefore, the negative pressure applied to the control valve 86 is determined by the ON duty ratio of the transistor 90. The controlled negative pressure of the pressure control valve 84 causes the exhaust pipe 10 to flow into the intake pipe 0.
The amount of EGR to 6 is controlled. Figure 4 is an overall configuration diagram of a control system using a microcomputer, which includes a central processing unit 102 (hereinafter referred to as CPU), a read-only memory 104 (hereinafter referred to as ROM), and a random access memory 106 (hereinafter referred to as ROM). (referred to as RAM) and an input/output circuit 108.
The CPU 102 calculates input data from the input/output circuit 108 using various programs stored in the ROM 104, and returns the calculation results to the input/output circuit 108 again. RAM 106 is used for intermediate storage necessary for these operations. CPU102,
ROM104, RAM106, input/output circuit 108
Exchange of various data between them is performed by a bus line 110 consisting of a data bus, a control bus, and an address bus. The input/output circuit 108 includes a first analog-to-digital converter 122 (hereinafter referred to as ADC1).
and a second analog-to-digital converter 12
4 (hereinafter referred to as ADC2) and angle signal processing circuit 1
26 and a discrete input/output circuit 128 (hereinafter referred to as DIO) for inputting and outputting 1-bit information. ADC1 has a battery voltage detection sensor 132
(hereinafter referred to as VBS) and cooling water temperature sensor 56 (hereinafter referred to as VBS)
(hereinafter referred to as TWS) and atmospheric temperature sensor 136 (hereinafter referred to as TAS)
), the adjustment voltage generator 138 (hereinafter referred to as VRS), and the throttle angle sensor 140 (hereinafter referred to as θTHS)
The outputs of the O ₂ sensor 142 (hereinafter referred to as O ₂ S) are added to the multiplexer 162 (hereinafter referred to as MPX), and the MPX 162 selects one of them and performs analog/digital conversion. The signal is input to a circuit 164 (hereinafter referred to as ADC). ADC1
The digital value that is the output of 64 is stored in register 166.
(hereinafter referred to as REG). In addition, the negative pressure sensor 144 (hereinafter referred to as VCS)
It is input to the ADC2, 124, is converted into a digital signal via the analog-to-digital conversion circuit 172 (hereinafter referred to as ADC), and is converted into a register 124 (hereinafter referred to as ADC).
REG). The angle sensor 146 (hereinafter referred to as ANGS) outputs a signal indicating a reference crank angle, for example, 180 degrees crank angle (hereinafter referred to as REF), and a signal indicating a minute angle, for example, 1 degree crank angle (hereinafter referred to as POS). The signal is applied to the angle signal processing circuit 126, where the waveform is shaped. DIO 128 includes an idle switch 148 that operates when the throttle valve 14 returns to the fully closed position.
(hereinafter referred to as IDLE-SW), top gear switch 150 (hereinafter referred to as TOP-SW), and starter switch 152 (hereinafter referred to as START-SW)
is entered. Flow rate sensor 24 (hereinafter referred to as AFS) is ADC2
is input to analog/digital/conversion circuit 1
72 (hereinafter referred to as ADC), it is digitally converted and set in a register 174 (hereinafter referred to as REG). Next, the pulse output circuit and control target based on the calculation results of the CPU will be explained. The injector control circuit (denoted as INJC) is a circuit that converts the digital value of the calculation result into a pulse output. Therefore, a pulse with a pulse width corresponding to the fuel injection amount
INJ is made with INJC1134, AND gate 11
36 to the injector 12. The ignition pulse generation circuit 1138 (hereinafter referred to as IGNC) has a register (hereinafter referred to as ADV) for setting the ignition timing and a register (hereinafter referred to as DWL) for setting the primary current energization start time of the ignition coil.
These data are set by the CPU. Generates a pulse IGN based on the set data,
AND gate 11 to amplifier 62 detailed in FIG.
Apply this pulse IGN via 40. The opening rate of the bypass valve 61 is determined by the control circuit (hereinafter referred to as
ISCC) 1142 to AND gate 1144
is controlled by a pulse ISC applied via. ISCC 1142 has a register ISCD for setting the pulse width and a register ISCP for setting the repetition pulse period. The EGR amount control pulse generation circuit 178 (hereinafter referred to as EGRC) that controls the transistor 90 that controls the EGR control valve 86 shown in FIG. 3 has a register that sets a value representing the duty of the pulse.
It has EGRD and a register EGRP for setting a value representing the pulse repetition period. This EGRC
The output pulse EGR of is applied to transistor 90 via AND gate 1156. Further, the 1-bit input/output signal is controlled by the circuit DIO128. IDLE-SW as input signal
signal, TOP-SW signal, and START-SW signal. Further, the output signal includes a pulse output signal for driving the fuel pump. This DIO has a register DDR192 for determining whether the terminal is used as an input terminal or an output terminal,
Register DOUT for latching output data
194 are provided. The mode register 1160 is a register (hereinafter referred to as MOD) that holds instructions for specifying various states inside the input/output circuit 108. For example, by setting an instruction to the mode register 1160, the AND gates 1136, 1140, 1144,
All 1156 are activated or deactivated. Like this MOD register 11
By setting the command to 60, INJC and
You can control the stop and start of IGNC and ISCC output. As mentioned above, DIO 128 is a 1-bit signal input/output circuit, and is a register (hereinafter referred to as DDR) 1 that holds data for determining input or output.
92 and a register 194 (hereinafter referred to as DOUT) for holding data to be output.
This DIO 128 outputs a signal DIO0 for controlling the fuel pump 32. FIG. 5 is a program system diagram of the control circuit of FIG. 4. When the power is turned on by a key switch (not shown), the CPU 102 enters a start mode and executes an initialization program (INITIALIZ) 204. Next, execute the monitoring program (MONIT) 206 and execute the BACK GROUND JOB 2.
Execute 08. This background job includes, for example, the EGR amount calculation task (EGR
CAL TASK) and a calculation task (hereinafter referred to as FISC) for the bypass valve 61 and injector 12 during warm-up operation. During the execution of this TASK, if an interrupt factor (hereinafter referred to as IRQ) occurs,
From the IRQ disclosure step 222, an IRQ factor analysis program 224 (hereinafter referred to as IRQ ANAL) is executed. Execute this IRQ (denoted as ANAL).
This IRQ ANAL program further handles the end interrupt of ADC1 (hereinafter referred to as ADC1 END IRQ).
Program 226 and ADC2 end interrupt processing (hereinafter referred to as ADC2 END IRQ) program 228
, a certain period elapsed interrupt processing (hereinafter referred to as INTV IRQ) program, and an engine stop interrupt processing (hereinafter referred to as INTV IRQ) program.
It consists of a program (hereinafter referred to as ENST IRQ) and issues a startup request (hereinafter referred to as QUEUE) to each task that needs to be started, which will be described later. Each program in this IRQ ANAL program 224 ADC1 END IRQ226 and ADC2
Each task to which a QUEUE is issued by each program of END IRQ 228 and INTV IRQ 230 is level zero task group 252 or level 1 task group 2.
54, level 2 task group 256, level 3 task group 258, or tasks constituting each task group. The task in which QUEUE is generated by the ENST IRQ program 232 is the engine stop processing task 262 (hereinafter ENST
(written as TASK). This ENST TASK26
2 is executed, the control system starts again.
mode and returns to the starting point 202. The task scheduler 242 sets the execution order of the tasks so that they are executed starting with the task in which the QUEUE is occurring or the task with the highest level among the tasks whose execution has been interrupted (here, level zero is the highest). decide. When the execution of the task group is completed, the completion report program 260 (hereinafter referred to as EXIT) reports the completion. Based on this completion report, the task group with the highest level among the task groups waiting for execution is executed next. When there are no more suspended tasks or QUEUE tasks, the task scheduler 242
The process then moves on to executing the background job 208 again. Furthermore, if an IRQ occurs while any of the level 0 task group to level 3 task group is being executed, the process returns to the starting point 222 of the IRQ processing program. Table 1 shows the activation of each task and its functions.

[Table] In this Table 1, IRQ ANAL
There are programs, TASK SCHDULER, and EXIT. These programs (hereinafter referred to as OS) are held at addresses A000 to A300 of the ROM 104 as shown in FIG. In addition, AD1 as a level zero program
There are IN, AD1ST, AD2IN, AD2ST, and RPMIN programs, usually 10 of INTV IRQ.
Started with [mSEC]. There are INJC, IGNCAL, and DWLCAL programs as level 1 programs, which are activated every 20 [mSEC] of INTV IRQ. A level 2 program is the LAMBDA program, which is activated every 40 [mSEC] of INTV IRQ. HOSEI as a level 3 program
There is a program and the INTV IRQ is 100 [mSEC]
is started every time. There are also EGRCAL and FISC programs as background jobs.
The above level zero program is PROG1 at address A70 of ROM104 in Figure 6.
It is stored in AAFF from 0. The level 1 program is the address of ROM104 as PROG2.
It is stored from AB00 to ABFF. level 2
The program is stored as PROG3 in addresses AE00 to AEFF of the ROM 104. The level 3 program is stored as PROG4 at addresses AF00 to AFFF in the ROM 104.
Also, background job programs are held in B000 to B1FF. The list of start addresses for each program from PROG1 to PROG4 above (see below)
SETMR) is held from B200 to B2FF, and values representing each program activation cycle from PROG1 to PROG4 (hereinafter referred to as TTM) are stored at addresses B300 to B3FF. Other data is stored at addresses B400 to B4FF of the ROM in FIG. 6 as necessary. Following that, data ADV.MAP and AF for calculation.
MAP and EGR.MAP are memorized respectively. Note that other detailed operations are not particularly relevant to the present invention and will therefore be omitted. Thus, according to the EEC mentioned above,
Most engine-related controls such as A/F control can be carried out appropriately, and it is possible to fully meet strict exhaust gas regulations, as well as provide an engine control device with excellent fuel ratio and driving feel. It has come to be adopted in many automobiles. By the way, since various actuators are used in cars equipped with such EEC, if any of these actuators malfunction, control operations will not be performed properly, and in extreme cases, it will be impossible to continue driving. This poses a problem in that the vehicle may become damaged or it may become dangerous to continue driving. For example, the bypass valve 61 (Figure 1) is the actuator of the idle speed control system ISC.
If something like this breaks down and the valve is left open, the engine speed will rise rapidly at idle, and in extreme cases, this can become a dangerous situation. Therefore, the conventional EEC has the disadvantage that if the actuator of the ISC fails, it becomes difficult to drive the vehicle and it is likely to cause a breakdown on the road. Additionally, related devices of this type include:
For example, the disclosure of Japanese Patent Application Laid-open No. 55-98625 can be mentioned. SUMMARY OF THE INVENTION An object of the present invention is to provide an ISC backup device which eliminates the above-mentioned drawbacks of the prior art and can prevent the idle speed from increasing rapidly even if the ISC actuator fails. In order to achieve this object, the present invention is characterized in that EGR is performed in an idle state when a failure of the actuator for ISC is detected. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a backup device for an idle speed control system according to the present invention will be described below with reference to the drawings. FIG. 7 is a flowchart illustrating the operation of an embodiment of the present invention. Note that even in this example
The overall configuration of the EEC is almost the same as the conventional EEC shown in Figures 1 to 6, but the operation shown in Figure 7 is different from that shown in Figure 4.
The only difference is that it is incorporated as one of the control programs of the microcomputer consisting of the CPU 102, ROM 104, etc., and in this case, the background job 208 shown in Table 1 and FIG. The device is configured so that this operation can be performed. Also, at this time, ISC is
It is programmed as an extension of FISC. When this flow starts, first, in step 1 (hereinafter referred to as S), it is checked whether the idle switch 148 (FIG. 4) is ON. As already explained, idle switch 14
8, when the accelerator pedal is released, the throttle valve 14 (first
This is a switch that turns ON when the switch (see figure) returns to the fully closed position. Therefore, when the determination result in S1 is NO, it indicates that the engine operating state is not in the idle state, and one of the conditions for stopping ISC and entering EGR is satisfied. Therefore, at this time, the program proceeds to S2, first setting the ISC data (ISCD) to zero to stop the ISC, and then checking other EGR conditions in S3. In addition,
Other conditions for entering EGR include, for example, whether the engine temperature is within a predetermined range. Therefore, if the result in S3 is NO, S
After setting the EGR data (EGRD) to zero through 4, exit to EXIT. Also, if the result in S3 is YES, EGR
First, in S5, EGRD is calculated, then in S6, EGRD is set and EXIT is executed.
Exit to. Note that the calculation of EGRD in S5 is performed by, for example, a map search from the intake air amount data AF and the engine speed N. Now, if the judgment result in S1 is YES,
After entering the ISC, it is first checked in S7 whether or not a flag indicating that an ISC output shot failure has occurred is set. If the judgment result in S7 is NO, proceed to the next S8 to calculate ISCD, and then proceed to S8.
Set EGRD to zero at step 9, and finally set EGRD to zero at step S10.
Sets ISCD and exits to EXIT. Therefore, normal ISC operation will be performed at this time. On the other hand, if the judgment result in S7 is YES, that is, a shoot (ground) failure has occurred in the ISC output, the bypass valve 61, which is the actuator of the ISC, becomes open and the rotation speed suddenly increases during idle. It means to have caused fear. Therefore, in this case, EGRD is passed through S11.
A predetermined value is set for . As a result, according to this embodiment, when a failure occurs in the actuator of the ISC and the bypass valve 61 becomes open, causing a sudden increase in the idle speed, a certain amount of exhaust gas is always recirculated. Therefore, it is possible to prevent the rotational speed from rapidly increasing during idling. Next, a failure detection operation of the above-described ISC (FISC) actuator will be explained. In this embodiment, when detecting a failure in an actuator, the determination of whether or not there is a failure is repeated not only once but multiple times, for example, five times, thereby detecting a temporary abnormal state that happened to occur at the time of failure determination. This system eliminates detection results that result in faults caused by noise that has entered the signal system, ensuring that only true faults can be detected, and therefore detecting faults according to the flowchart in Figure 8. The configuration is such that a detection operation is performed. Therefore, when the failure detection program of the background job 208 is entered, the operation shown in FIG. 8 is performed, and first, in S80, a failure determination of the ISC actuator is performed. Note that this failure determination will be described later. If the determination result in S80 is NG, that is, a failure, the NG counter is incremented toward S81. This NG counter has a judgment result
This is to count the number of times the result is NG. Next, the process advances to S82 to check whether the content of this NG counter is 5 or not. by the way,
Now, if the determination result in S80 is NG for the first time, the result in S82 will naturally be NO, so the flow exits directly to EXIT and ends this flow. If the result in S80 becomes NG again when the flow starts the next time, the above operation is repeated, and the NG counter is incremented by 1 each time in S81. Therefore, each time we enter the operation of this flow,
If the determination result in S80 is NG, that is, if the fault condition continues and is detected five times, then the determination result in S82 becomes YES. Therefore, at this time, S83
Go to , set the contents of the NG counter to 0, and then press S.
EXIT after setting the failure flag at step 84.
Exit to. On the other hand, if the result in S80 is OK, that is, no failure has been detected, the process goes to S85 to check the contents of the NG counter, and if it has not reached 0, that is, the result is NO, the process goes to S86 to check the NG counter. After setting the contents to 0, proceed to S87. Further, if the result in S85 is determined to be YES, the process directly advances to S87 to check whether or not the failure flag is set.If the result is YES, the failure flag is cleared after passing through S88.
Exits to EXIT, and if NO, immediately from S87
Exit to EXIT. As a result of performing the operations according to the flowchart in FIG.
Since the counter is reset to 0 and the failure flag is cleared, the failure flag is set through S84 only when the judgment result in S80 is NG five times in a row, that is, there is an abnormality. This makes it possible to eliminate failure flags from being set due to erroneous detections due to temporary abnormalities or noise. Note that if the contents of the NG counter in S82 are set to another number, the number of times the check is performed can be set to an arbitrary number accordingly. In addition, in this embodiment, after the failure flag has been set and NG processing has been performed five times in a row,
Even if the result at S80 becomes OK, the failure flag is set again only when NG occurs five times in a row, but once the failure flag is set, the determination becomes OK. The reason for this is that there are more cases where an abnormality is determined to be normal due to false detection than when the abnormality disappears, so if the judgment becomes NG after that, immediately reset the failure flag. You can do it like this. In other words, in this case, even if the result of S80 is not NG five times in a row, S8 is immediately executed just once.
1 through S84. To this end, for example, a step for setting the content of the NG counter to 4 may be provided after S88. Next, an embodiment of the ISC actuator failure determination system shown in S80 of FIG. 8 will be described with reference to FIGS. 9 and 10. FIG. 9 shows an embodiment of the failure detection circuit, in which 209 is the input of the ISC signal, 210 and 211 are the outputs of the detection signals PA6 and PA7, and 212 is the test signal.
PB7 input, 215 is the output to which the wire harness from bypass valve 61 is connected, Q21
3. Q214 is a Darlington-connected output transistor, D ₁ and D ₂ are Zener diodes, R ₁ ~
R ₆ is the resistance. FIG. 10 is a flowchart showing the operation of the judgment system using this fault detection circuit, which is included in S80, which is a part of the flowchart in FIG. It is executed as follows. When entering this flow, first in S20 the detection signal is
PA6 and PA7 are read, and then it is checked in S21 whether the signal PA6 is 0 or 1. Then, when the result becomes 1, the signal is
Check whether PA7 is 0 or 1, and if the result is 1, it is assumed that there is no abnormality and exits successfully. In other words, signal PA6
is 1, which means that the signal ISC is 1, so it is normal for both transistors Q213 and Q214 to be on, so transistor Q21
5 should be off, so at this time the signal
If PA7 is also 1, it means that there is no abnormality. Furthermore, if the result becomes 0 in S22, this indicates that one or both of transistors Q213 and Q214 is open, so S2
Proceed to step 3 and prepare to set the defective flag.
Passed out in NG. On the other hand, if the result in S21 becomes 0, the next step is S2.
Proceed to step 4, check signal PA7, and if it becomes 0, proceed to OK. In other words, if signal PA6 is 0, signal ISC
is 0, transistors Q213 and Q214 are off,
Therefore, transistor Q215 should be on, and therefore, if signal PA7 is also 0, it is in a normal state. However, if the result in S24 becomes 1, the next S
25, and connect the test signal PB7 of terminal 212 to 1.
Then read the signal PA7 in S26, and then read the signal PA7 in S26.
7, it is checked whether this signal PA7 is 1 or 0. and,
If the result becomes 1, preparations are made to set the output short failure flag at S28, and then the process exits to NG. Further, if the result in S27 becomes 0, the process goes to S29, where the harness open defect flag is prepared to be set, and the process exits to NG. In other words, if signal PA6 is 0, transistor Q2
13 and Q214 should be off and transistor Q215 should be on, so signal PA7 must be 0. However, signal PA7 becomes 1, which means that the base of transistor Q215 becomes 0.
It means becoming. Therefore, when the signal PB7 is set to 1 in S25, if the signal PA7 does not become 0, a signal is sent to the base of the transistor Q215.
Since this means that PB7 is not given, it can be seen that the output is shot. Also, if the signal PA7 becomes 0 at this time, it means that the signal PB7 is applied to the base of the transistor Q215,
Therefore, it means that no voltage has been applied from the power supply +B through the solenoid valve 61 until then, and it is determined that the harness is open. In addition, in the embodiment shown in FIGS. 9 and 10,
Bypass valve 61 which is an actuator for ISC
Although the configuration is such that it is possible to detect defects other than the output shot failure, when these defects occur, the bypass valve 61 simply remains closed and does not open, and the rotation speed increases rapidly during idle. There's no fear. However, in this case, backup by EGR has no effect, so the above embodiment deals only with output short failure, and even if other failures are detected, no special action is taken to deal with them. However, it may be configured to issue a warning when the above defect is detected. As explained above, according to the present invention, in the EEC of an automobile engine equipped with an idle speed control system, it is possible to prevent the idle speed from rapidly increasing even if a failure occurs in the actuator for controlling the idle speed. Therefore, it is possible to provide a backup device in the EEC that does not make the operation of vehicles or the like dangerous or require the operation to be stopped.

[Brief explanation of drawings]

Figures 1 to 6 are diagrams showing an example of an electronic control system applied to a fuel injection type internal combustion engine. Figure 1 is a sectional view of the engine including a part of the control system, and Figure 2 is a sectional view of the engine. Schematic diagram of the ignition system, 3rd
The figure is a schematic diagram of the exhaust gas recirculation system, Figure 4 is a block diagram of the overall configuration of the control system, Figure 5 is a diagram of its program system, Figure 6 is a diagram of the memory configuration showing program contents, and Figure 7 is the invention of the present invention. FIG. 8 is a flowchart illustrating an embodiment of the failure determination operation,
FIG. 9 is a circuit diagram showing an embodiment of the failure determination system, and FIG. 10 is a flowchart for explaining its operation. 61... Bypass valve serving as an actuator for the idle speed control system, 84... Pressure control valve for the exhaust gas recirculation system, Q213, Q214...
...Output transistor for driving the bypass valve.

Claims (1)

[Claims] 1. In an electronically controlled engine control device equipped with an idle speed control system and an exhaust gas recirculation system, failure detection means detects an abnormality in the actuator means for controlling the idle speed, and detects that the engine is in an idle state. and a recirculation flow rate control actuator means for controlling the amount of exhaust gas recirculated. The idle rotation speed is controlled by operating the recirculation flow rate control actuator means in an idling state according to the data of the failure detection means. A backup device for an idle rotation speed control system, characterized in that it is configured to control an idle operating state in the event of a system failure.