JPS6349274B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a pattern recognition device, particularly a pattern recognition device that extracts features of figures such as characters, figures, and symbols, and recognizes the figures, in which a category is determined from the extracted features. In the recognition circuit section
The present invention relates to a pattern recognition device that uses a multi-stage memory such as a ROM, and accesses the memory using the extracted characteristics to uniquely determine a category.

Conventionally, in pattern recognition devices, the first
The configuration described below with reference to the figures and the configuration described below with reference to FIG. 2 are considered. The former form is
Although it has the advantage that it is possible to provide flexibility in the recognition processing mode by changing or updating the contents of the dictionary section, it is also possible to provide flexibility in the recognition processing mode by changing or updating the contents of the dictionary section. It is necessary to check the standard features corresponding to all the categories, which poses a problem in terms of improving processing speed. Furthermore, the latter form is extremely advantageous in terms of processing speed because a desired category can be determined mathematically based on one feature set in the feature buffer, but on the other hand, the This method has major drawbacks, such as the circuit configuration becoming enormous as the number of categories increases, and the difficulty of providing flexibility in the recognition processing mode. Because of the major drawbacks of the latter form, the former form has been widely adopted.

An object of the present invention is to provide a pattern recognition device which solves the above-mentioned difficulties of the latter form and greatly improves the processing speed. In a pattern recognition device that extracts the features of a figure to be recognized and recognizes the figure to be recognized from the features, each memory chip in each stage stores memory chip selection information for the next stage, and each memory chip in the last stage stores the memory chip selection information for the next stage. The recognition circuit section includes a multi-stage configuration memory that stores the category information of the figure and uses feature data corresponding to the extracted features as an address, and the recognition circuit section stores each part of the address in the memory chip of each stage. The present invention is characterized in that the multi-stage configuration memory is accessed as an inner address, category information of the figure to be recognized is extracted, and the figure to be recognized is recognized based on the retrieved category information of the figure to be recognized. This will be explained below with reference to the drawings.

FIG. 1 shows a form of a conventional pattern recognition device, and FIG. 2 shows an example of a form to which the pattern recognition device of the present invention is applied. Figures 3A, B, and C and Figures 4A and B are explanatory diagrams explaining the concept of the recognition circuit section used in the pattern recognition device of the present invention, respectively, and Figure 5 is a recognition circuit used in the pattern recognition device of the present invention. 1 shows an example configuration of the section.

In FIG. 1, numeral 1 is an input video reading section which converts the figure to be recognized into an electrical signal, and numeral 2 is a feature extraction circuit section which extracts predetermined features based on the output from the input video reading section 1. 3 is a feature buffer in which the extracted features (actually binary data patterns expressing the features) are set; 4 is a dictionary section that contains all categories to be recognized. Reference numeral 5 represents a matching circuit section which matches the contents of the feature buffer 3 with the standard features individually read out from the dictionary section 4.

The form shown in FIG. 1 has been widely adopted in the past, and a detailed explanation will be omitted, but in the case of the form shown in FIG. It becomes necessary to match each standard feature individually, which limits the improvement in processing speed.

In FIG. 2, numerals 1, 2, and 3 correspond to those in FIG. ing.

When performing pattern recognition, one category is determined as much as possible based on the contents of the feature buffer 3.
By performing mathematical logical processing on the contents of
This does not mean that it is impossible to configure the recognition circuit section 6 that determines one category. However, if an attempt is made to construct the recognition circuit section 6 using a general logic circuit, the circuit configuration will become complicated.Moreover, considering the case where the feature to be set in the feature buffer 3 is to be increased by one bit, the recognition circuit section 6
As can be seen from the fact that the circuit configuration of the circuit is changed, there is little flexibility in changing the processing.

The present invention uses, for example, a ROM as the recognition circuit section 6 shown in FIG. We are trying to make it easier to improve. 3rd below
The concept will be explained with reference to the figures and FIG.

Generally, in a pattern recognition apparatus, a feature extraction circuit section 2 extracts features and sets them in a feature buffer 3, as shown in FIGS. Then, as shown in FIG. 3A, when the features are given by {x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ , x ₇ }, the classification is done in a tree based on the features. It is being done. That is, for example, if the data x ₁ in the feature is logical "0", it is determined that the category to be determined is one of the categories y ₁ , y ₂ , y ₃ , and y ₄ . Then, the data x ₃ , x ₆ , x ₇ in the feature are ignored, so to speak, and then it is checked whether the data x ₂ in the feature is logical "0" or "1" and it is determined as "0".
If so, the results will be narrowed down to category y ₁ or y ₂ .

When performing classification as shown in Figure 3A,
As shown in FIG. 3B, the ROM ₇ is accessed using the data x ₁ , x ₂ . . . can be read out. In this case, the relationship between each address of the ROM 7 and the content (representing the data category) stored at the address is shown in FIG. 3C. In FIG. 3C, the cross indicates don't care.

That is, for _example , if the _address bits, _{, and} Data “000” representing
is stored.

In the case shown in FIG. 3, categories y ₁ to y ₈ are recognized, but if the number of categories is, for example, 16, it may be configured as shown in FIG. 4. In addition, in Figure 4, 8-1 and 8-2 are
ROM, 9 represents the note circuit, and CS represents the chip.
Represents the select terminal.

That is, one of the ROMs 8-1 and 8-2 is selected based on the bit corresponding to the feature x ₁ , and the ROM 8-1 side has the features x ₂ , x ₄ , x ₅ , x ₈ ,
Bits corresponding to x ₉ , x ₁₀ , x ₁₁ ,...
is supplied as address information. ROM8-2
The same holds true for the ROM 8-1 and the ROM 8-2, and the read output from the ROM 8-1 and the read output from the ROM 8-2 are taken out in the form of a wired-OR.

FIG. 5 shows an embodiment of the recognition circuit according to the present invention, which incorporates the concept explained with reference to FIGS. 3 and 4 above.

In FIG. 5, 6 is a recognition circuit section, 9-0, 9
-1 represents the first stage ROM, 9-00 to 9-Op represent the second stage ROM, and 9-000 to 9-Orq represent the third stage ROM. In the case shown, the first stage
The read output from ROM9-0 is supplied to the chip select terminal CS of the second stage ROM, and the second stage ROM
The read outputs from the ROMs 9-00 to 9-Op are supplied to the chip select terminal CS of the third stage ROM, and the category is determined by the read outputs from the third stage ROM.

Of course, it is generally free to add a simple AND circuit, OR circuit, etc. to the readout output from the i-th stage ROM as necessary. Furthermore, in the case of a pattern recognition device, if it is still not possible to determine one final category even after classification by major classification, classification processing is performed so that classification is performed by small classification using even more detailed features. It is also done in a hierarchical manner. In such a case, a plurality of recognition circuit units 6 shown in FIG. 5 may be connected in cascade as necessary.

As explained above, according to the present invention, a memory such as a ROM is used as the structure of the recognition circuit section 6 shown in FIG. 2, so that the circuit structure is simplified. In addition, in the design process of a pattern recognition device, when the recognition processing mode is modified or when an additional bit is added to the feature set in the feature buffer, the ROM may be replaced or the ROM may be changed as necessary. This can be easily dealt with by increasing the number of stages, and the judgment dictionary can be changed at the design stage or during operation in the field. Furthermore, since one piece of read data from one chip memory is used as a chip select signal in the next chip memory, generally 1:n branching (where n is, for example, 3
(integers greater than or equal to) can be expanded into a tree.

[Brief explanation of the drawing]

FIG. 1 shows a form of a conventional pattern recognition device, and FIG. 2 shows an example of a form to which the pattern recognition device of the present invention is applied. Figures 3A, B, and C and Figures 4A and B are explanatory diagrams explaining the concept of the recognition circuit section used in the pattern recognition device of the present invention, respectively, and Figure 5 is a recognition circuit used in the pattern recognition device of the present invention. The configuration of one embodiment is shown. In the figure, 1 is an input video reading section, 2 is a feature extraction circuit section, 3 is a feature buffer, 6 is a recognition circuit section, 7,
8 and 9 each represent a ROM.

Claims (1)

[Claims] 1. In a pattern recognition device that extracts features of a figure to be recognized based on a video signal of the figure to be recognized and recognizes the figure to be recognized from the features, each memory chip in each stage stores memory chip selection information for the next stage. Then, each memory chip in the final stage stores category information of the figure to be recognized,
The recognition circuit section includes a multi-stage configuration memory that uses feature data corresponding to the extracted feature as an address, and the recognition circuit section uses each part of the address as an address in the memory chip of each stage to read the multi-stage configuration memory. A pattern recognition device characterized by accessing, extracting category information of a recognition target figure, and recognizing the recognition target figure based on the retrieved category information of the recognition target figure.