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JPS6349378B2 - - Google Patents
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JPS6349378B2 - - Google Patents

Info

Publication number
JPS6349378B2
JPS6349378B2 JP58179602A JP17960283A JPS6349378B2 JP S6349378 B2 JPS6349378 B2 JP S6349378B2 JP 58179602 A JP58179602 A JP 58179602A JP 17960283 A JP17960283 A JP 17960283A JP S6349378 B2 JPS6349378 B2 JP S6349378B2
Authority
JP
Japan
Prior art keywords
film
metal film
bump
forming
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58179602A
Other languages
Japanese (ja)
Other versions
JPS6072249A (en
Inventor
Katsuhiko Yabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58179602A priority Critical patent/JPS6072249A/en
Publication of JPS6072249A publication Critical patent/JPS6072249A/en
Publication of JPS6349378B2 publication Critical patent/JPS6349378B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は集積回路の製造方法に関し、特に外部
端子である電極用金バンプを有する集積回路の製
造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing an integrated circuit having gold bumps for electrodes serving as external terminals.

〔従来技術〕[Prior art]

従来、集積回路の電極用金バンプ及び表面保護
用のポリイミド被膜の形成は、第1図〜第3図に
示す如く実施されている。第1図はウエーハ上に
第1バンプ並びに第2バンプの形成された集積回
路製造工程の断面図、第2図は表面保護とバンプ
のはがれ防止のためにポリイミド被膜を形成した
集積回路の平面図、第3図は第2図のA−A′断
面図である。
Conventionally, gold bumps for electrodes of integrated circuits and polyimide coatings for surface protection have been formed as shown in FIGS. 1 to 3. Figure 1 is a cross-sectional view of an integrated circuit manufacturing process in which first and second bumps are formed on a wafer, and Figure 2 is a plan view of an integrated circuit in which a polyimide film is formed to protect the surface and prevent bumps from peeling off. , FIG. 3 is a sectional view taken along line A-A' in FIG. 2.

第1図に示すように、拡散、絶縁膜形成、配線
工程の終了したウエーハの絶縁膜5の上に接着層
であるTi膜1、バリヤ層であるPt膜2を付着さ
せた後その上に第1バンプ3、第2バンプ4を金
メツキで形成する。
As shown in FIG. 1, a Ti film 1 as an adhesive layer and a Pt film 2 as a barrier layer are deposited on the insulating film 5 of the wafer after the diffusion, insulating film formation, and wiring processes have been completed. The first bump 3 and the second bump 4 are formed with gold plating.

次いで、第2図、第3図に示すように表面保護
並びにバンプのはがれ防止のためポリイミド被膜
6を形成する。ポリイミド被膜はウエーハ上にポ
リイミド被膜を塗布形成した後、露光、現像によ
り第2バンプ4上のポリイミド被膜を除去し、第
1バンプ3の端部を覆うように選択除去する。し
かし、第2バンプ4の厚さは10〜25μmと厚く異
常にきつい段差のため、所望のパターン通りの選
択除去が困難で、第1バンプ3の端部を覆わない
ばかりか、第2バンプ4以外のウエーハ表面を露
出して形成されることが多い。
Next, as shown in FIGS. 2 and 3, a polyimide film 6 is formed to protect the surface and prevent the bumps from peeling off. After forming the polyimide film by coating on the wafer, the polyimide film on the second bumps 4 is removed by exposure and development, and is selectively removed so as to cover the ends of the first bumps 3. However, since the second bump 4 has a thickness of 10 to 25 μm and has an abnormally tight step, it is difficult to selectively remove the second bump 4 according to a desired pattern. It is often formed by exposing the other wafer surface.

このように形成された集積回路では第1バンプ
3の端部が十分覆われていないのでポリイミド被
膜6の第1の役割であるバンプのはがれ防止の役
に立たない。また第1バンプ3及びバンプ以外の
ウエーハの一部が露出されているので表面保護の
面でも不十分であるという欠点があつた。
In the integrated circuit formed in this manner, the ends of the first bumps 3 are not sufficiently covered, so that the polyimide coating 6 is useless in preventing the bumps from peeling off, which is the first role. Furthermore, since the first bumps 3 and a portion of the wafer other than the bumps are exposed, there is a drawback that surface protection is insufficient.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を除去し、ポリイミ
ド被膜は第1バンプ端部を十分覆い、バンプのは
がれを防止すると共に、表面保護膜としての役割
も十分果すことが出来る集積回路の製造方法を提
供することにある。
An object of the present invention is to provide a method for manufacturing an integrated circuit in which the above-mentioned drawbacks are eliminated, the polyimide film sufficiently covers the end of the first bump, prevents the bump from peeling off, and also sufficiently plays the role of a surface protection film. It is about providing.

〔発明の構成〕[Structure of the invention]

本発明の集積回路の製造方法は、拡散、絶縁
膜、配線を形成したウエーハの前記絶縁膜の上に
密着層としての第1の金属膜、バリヤ層としての
第2金属膜及びAuの第1バンプを順次形成する
第1の工程と、前記第1バンプの全部又は一部上
に開孔部を持つポリイミド被膜を形成する第2の
工程と、前記ポリイミド被膜の形成されたウエー
ハ全面に化学薬品でエツチング可能な金属より成
る第3の金属膜を形成する第3の工程と、前記第
3の金属膜の形成されたウエーハ上にホトレジス
ト膜を全面被着し前記ポリイミド膜の開孔部と重
なる開孔部を形成する第4の工程と、前記ホトレ
ジスト膜をマスクとし前記第3の金属膜を電極と
して電解金メツキを行つて第2バンプを形成する
第5の工程と、前記ホトレジスト膜をポリイミド
被膜を溶解しない有機性剥離剤で剥離する第6の
工程と、前記第3の金属膜のうちバンプ以外の部
分をエツチング除去する工程とを含んで構成され
る。
The method for manufacturing an integrated circuit of the present invention includes forming a first metal film as an adhesion layer, a second metal film as a barrier layer, and a first metal film of Au on the insulating film of a wafer on which diffusion, an insulating film, and wiring have been formed. A first step of sequentially forming bumps, a second step of forming a polyimide film having openings on all or part of the first bumps, and applying a chemical agent to the entire surface of the wafer on which the polyimide film is formed. a third step of forming a third metal film made of a metal that can be etched by etching, and depositing a photoresist film over the entire surface of the wafer on which the third metal film is formed so as to overlap with the openings of the polyimide film. a fourth step of forming an opening; a fifth step of forming a second bump by electrolytic gold plating using the photoresist film as a mask and the third metal film as an electrode; The method includes a sixth step of removing the film using an organic remover that does not dissolve the film, and a step of etching away portions of the third metal film other than the bumps.

〔実施例の説明〕[Explanation of Examples]

以下、本発明の実施例について、図面を参照し
て説明する。
Embodiments of the present invention will be described below with reference to the drawings.

第4図a〜gは本発明の一実施例を説明するた
めの工程順に示した断面図である。
FIGS. 4a to 4g are cross-sectional views showing the steps in order to explain an embodiment of the present invention.

第4図aに示すように、拡散、絶縁膜及び配線
工程を終了した集積回路表面の絶縁膜5の上にバ
ンプと絶縁膜との密着層として0.1μmのTi膜1、
Tiと金バンプのバリヤ層としての0.1μm厚のPt
膜2、及び金の第1バンプ3を形成する。
As shown in FIG. 4a, on the insulating film 5 on the surface of the integrated circuit after the diffusion, insulating film and wiring processes are completed, a 0.1 μm Ti film 1 is placed as an adhesion layer between the bump and the insulating film.
0.1μm thick Pt as barrier layer between Ti and gold bumps
A film 2 and a first gold bump 3 are formed.

次に、第4図bに示すように、ウエーハの表面
にポリイミド被膜を被着させ、第1バンプ3上に
第2バンプ形成用の開孔部9を形成する。このと
き第1バンプ3の端部はポリイミド被膜6により
確実に覆われるように形成する。
Next, as shown in FIG. 4b, a polyimide film is applied to the surface of the wafer, and openings 9 for forming second bumps are formed on the first bumps 3. At this time, the ends of the first bumps 3 are formed to be reliably covered with the polyimide coating 6.

次に、第4図cに示すように、後の工程で化学
薬品により容易にエツチングされ、また金メツキ
の電極として好都合な金属として、Pd、Ni、Cu
からなる群から選ばれた金属として0.1μm厚の
Pd膜7を全面にスパツタにより形成する。
Next, as shown in Figure 4c, metals such as Pd, Ni, and Cu, which are easily etched by chemicals in later steps and are convenient as electrodes for gold plating, are used.
0.1 μm thick metal selected from the group consisting of
A Pd film 7 is formed on the entire surface by sputtering.

次に、第4図dに示すように全表面にホトレジ
スト膜8を塗布した後ポリイミド被膜6の開孔部
9と重なる開孔部10を形成するようにホトレジ
スト膜8をパターニングする。
Next, as shown in FIG. 4d, a photoresist film 8 is coated on the entire surface, and then the photoresist film 8 is patterned to form openings 10 that overlap the openings 9 of the polyimide coating 6.

次に、第4図eに示すように、さきに形成した
Pd膜7を電極として、ホトレジスト膜開孔部1
0に電解金メツキにより20μm厚の第2バンプ4
を形成する。
Next, as shown in Figure 4e, the previously formed
Using the Pd film 7 as an electrode, the photoresist film opening 1
A second bump 4 with a thickness of 20 μm is formed by electrolytic gold plating.
form.

次に、第4図fに示すように、ウエーハ上のホ
トレジスト膜8を剥離液で剥離除去する。
Next, as shown in FIG. 4f, the photoresist film 8 on the wafer is removed using a stripping solution.

次いで、第4図gに示すように、Pd膜7のう
ち、第2バンプ以外の部分を塩化第二鉄、塩酸等
によるPdエツチング液でエツチング除去する。
Next, as shown in FIG. 4g, the portions of the Pd film 7 other than the second bumps are removed by etching with a Pd etching solution containing ferric chloride, hydrochloric acid, or the like.

以上の工程によつて、電極の金バンプ及び保護
ポリイミド被膜が形成できる。
Through the above steps, the gold bumps of the electrodes and the protective polyimide coating can be formed.

以上形成されたポリイミド被膜は従来のように
第2バンプ形成後でなく、薄い第1バンプ形成後
に形成するのでホトレジストのパターニングは正
確に実施することができ、第1バンプの端部をポ
リイミド被膜で十分カバーすることができ、従つ
て絶縁層との間でのはがれを確実に防止すること
ができる。また同様の理由によりウエーハ面も露
出することがないのでポリイミド被膜の保護膜と
しての役割も十分果すことが可能である。
The polyimide film formed above is formed after the thin first bump is formed, not after the second bump is formed as in the conventional case, so the photoresist patterning can be carried out accurately, and the end of the first bump can be covered with the polyimide film. Sufficient coverage can be achieved, and peeling from the insulating layer can therefore be reliably prevented. Further, for the same reason, the wafer surface is not exposed, so it can sufficiently serve as a protective film for the polyimide film.

なお、上記実施例では第1金属膜としてTi膜、
第2金属膜としてPt膜を使用したが、これに限
定されるものではなく第1金属膜としてはCr、
NiCr、Ta、Mo、第2金属膜としては、Pd、Ni
の金属膜が同様に適用することが出来る。
Note that in the above embodiment, the first metal film is a Ti film,
Although a Pt film was used as the second metal film, it is not limited to this, and the first metal film may be Cr,
NiCr, Ta, Mo, second metal film: Pd, Ni
metal films can be applied as well.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、バンプ
のはがれが少なく、表面保護効果の大きい集積回
路を容易に製造することができる。
As described above, according to the present invention, it is possible to easily manufacture an integrated circuit with less peeling of bumps and a high surface protection effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のウエーハ上に第1バンプ並びに
第2バンプの形成された工程の集積回路の断面
図、第2図は従来の表面にポリイミド被膜の形成
された集積回路の平面図、第3図は第2図のA−
A′断面図、第4図a〜gは本発明の一実施例を
説明するための工程順に示した断面図である。 1……Ti膜、2……Pt膜、3……第1バンプ、
4……第2バンプ、5……絶縁膜、6……ポリイ
ミド被膜、7……Pd膜、8……ホトレジスト膜、
9,10……開孔部。
FIG. 1 is a cross-sectional view of an integrated circuit in a conventional process in which first and second bumps are formed on a wafer, FIG. 2 is a plan view of a conventional integrated circuit in which a polyimide film is formed on the surface, and FIG. The figure is A- in Figure 2.
A' sectional view and FIGS. 4a to 4g are sectional views shown in the order of steps for explaining an embodiment of the present invention. 1...Ti film, 2...Pt film, 3...first bump,
4... Second bump, 5... Insulating film, 6... Polyimide film, 7... Pd film, 8... Photoresist film,
9, 10... Opening part.

Claims (1)

【特許請求の範囲】 1 拡散、絶縁膜、配線を形成したウエーハの前
記絶縁膜の上に密着層としての第1の金属膜、バ
リヤ層としての第2金属膜及びAuの第1バンプ
を順次形成する第1の工程と、前記第1バンプの
全部又は一部上に開孔部を持つポリイミド被膜を
形成する第2の工程と、前記ポリイミド被膜の全
表面に化学薬品でエツチング可能な金属より成る
第3の金属膜を形成する第3の工程と、前記第3
の金属膜の形成されたウエーハ上にホトレジスト
膜を全面被着し前記ポリイミド被膜の開孔部と重
なる開孔部を形成する第4の工程と、前記ホトレ
ジスト膜をマスクとし前記第3の金属膜を電極と
して電解金メツキを行つて第2バンプを形成する
第5の工程と、前記ホトレジスト膜をポリイミド
被膜を溶解しない有機性剥離剤で剥離する第6の
工程と、前記第3の金属膜のうちバンプ以外の部
分をエツチング除去する工程とを含むことを特徴
とする集積回路の製造方法。 2 第1の金属膜がTi膜、第2の金属膜がPt膜、
である特許請求の範囲第1項記載の集積回路の製
造方法。 3 化学薬品でエツチング可能な金属がPd、Ni、
Cuからなる群から選ばれる特許請求の範囲第1
項記載の集積回路の製造方法。
[Claims] 1. A first metal film as an adhesion layer, a second metal film as a barrier layer, and a first bump of Au are sequentially formed on the insulating film of a wafer on which diffusion, an insulating film, and wiring have been formed. a second step of forming a polyimide film having openings on all or part of the first bump; a third step of forming a third metal film consisting of the third metal film;
a fourth step of depositing a photoresist film over the entire surface of the wafer on which the metal film has been formed and forming an opening that overlaps with the opening of the polyimide film; using the photoresist film as a mask, forming the third metal film; a fifth step of forming a second bump by electrolytic gold plating using the metal film as an electrode; a sixth step of removing the photoresist film with an organic stripping agent that does not dissolve the polyimide film; A method of manufacturing an integrated circuit, comprising the step of etching away portions other than the bumps. 2 The first metal film is a Ti film, the second metal film is a Pt film,
A method for manufacturing an integrated circuit according to claim 1. 3 Metals that can be etched with chemicals include Pd, Ni,
Claim 1 selected from the group consisting of Cu
A method for manufacturing an integrated circuit as described in Section 1.
JP58179602A 1983-09-28 1983-09-28 Manufacture of integrated circuit Granted JPS6072249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58179602A JPS6072249A (en) 1983-09-28 1983-09-28 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58179602A JPS6072249A (en) 1983-09-28 1983-09-28 Manufacture of integrated circuit

Publications (2)

Publication Number Publication Date
JPS6072249A JPS6072249A (en) 1985-04-24
JPS6349378B2 true JPS6349378B2 (en) 1988-10-04

Family

ID=16068609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58179602A Granted JPS6072249A (en) 1983-09-28 1983-09-28 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS6072249A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166542A (en) * 1987-12-22 1989-06-30 Fujitsu Ltd Manufacture of semiconductor device
JP2003006813A (en) * 2001-06-20 2003-01-10 Shinka Jitsugyo Kk Thin film magnetic head and its manufacturing method

Also Published As

Publication number Publication date
JPS6072249A (en) 1985-04-24

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