JPS6349939B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a differential decoding circuit using orthogonal multilevel amplitude modulation. In particular, the present invention provides a device that can correctly perform differential decoding for inversion of signal polarity between input and output that occurs in the automatic equalizer when the receiving side device includes an automatic equalizer. . The signal of the orthogonal multilevel amplitude modulation method is demodulated by carrier waves whose phases are orthogonal to each other, and
signals (referred to as P channel and Q channel here) are obtained. Generally, in order to deal with uncertainty in the reproduced carrier wave phase of a receiving side device, a transmitting device using orthogonal multilevel amplitude modulation performs differential code operation to make a data signal correspond to a phase difference of carrier waves. The receiving device performs a differential decoding operation to reproduce a data signal from the phase difference of the received signals. Furthermore, in recent years, there has been a trend toward multilevel modulation signals in order to effectively utilize frequency bands. As multileveling progresses, the amplitude distortion and delay distortion of the transmission path will be reduced.
Signal quality deteriorates significantly, and it is necessary to perform relief using an automatic equalizer or the like on the receiving side. Various types of automatic equalizers are known, but some of them have different polarities between the input and output of the equalizer for the two signal P channels and Q channels mentioned above. There are uncertainties. If a conventional differential decoder is applied as is to such an automatic equalizer, data signals cannot always be reproduced correctly. The present invention improves this, and even when the polarity of the signal is uncertain between the input and output of the automatic equalizer,
It is an object of the present invention to provide a differential decoding circuit that always enables correct signal reproduction. That is, in the present invention, for two signals demodulated by carrier waves whose phases are orthogonal to each other based on a polarity determination signal detected by an automatic equalizer, (a) (b) means for individually modifying the signal which has undergone polarity reversal in the automatic equalizer; (c) two signals at the input of the differential decoder; (d) means for interchanging two signals at the output end of the differential decoder; This will be explained in more detail using drawings. FIG. 1 is a conceptual diagram showing the configuration of a circuit according to an embodiment of the present invention. The signal applied to the input signal IN is applied to a known orthogonal multilevel amplitude demodulator 1 to obtain two output signals D _p and D _q . These signals D _p and D _q pass through an automatic equalizer 2 and become signals X _p and X _q . Further, these signals X _p and X _q become signals Y _p and Y q via a conversion circuit 3 according to the present invention, and are converted into signals Y p and Y _q by a known differential decoder 4.
The signals of the two channels S _p ,
Get S _q . Here, the polarity of the input and output of the automatic equalizer 2 is not determined depending on its type, and if the phase difference of carrier waves between adjacent time slots is Δθ, there are four types shown in the table corresponding to this phase difference Δθ. There is an uncertain difference.

[Table] According to this Gray code, states (), (),
For () and ( ₎ , respectively _, () X _p = D _p , X _q = D _q () X _p = _{D p} , _{X q = q} ( ₎ = _p , X _q = _q . The symbol indicates the reversal of polarity with respect to the state (). Now, in order to perform differential decoding correctly, the above phase angle Δθ must be set to 0, π/2, π, 3π/2 in the counterclockwise direction.
When looking at this, the order of (X _p , X _q ) becomes (0,
0), (0, 1), (1, 1), (1, 0). Of the four states above, () and () satisfy this condition, and in the case of () and (), the signs of Δθ=π/2 and Δθ=3π/2 are switched, so It is assumed that the phase rotation of the phase angle Δθ is erroneously reversed, and at the output end of the differential decoder 4, S _q is in the P channel and Q
S _p will appear on the channel. In order to do this correctly, it is necessary to identify the above states () and (), and (a) further invert the polarity of a predetermined one of the signals X _p and X _q ; (b ) Correcting the signal whose polarity has been reversed in the automatic equalizer 2 individually, (c) Swapping the PQ channels at the input end of the differential decoder 4, (d) Output of the differential decoder 4 You can either swap the PQ channels at the end. In FIG. 1, PL is a polarity determination signal, which includes information as to whether or not polarity inversion has occurred in the automatic equalizer 2, and which signal has polarity inversion. To obtain the polarity determination signal from the automatic equalizer 2,
As an example, a circuit can be used that compares the control voltage of a multiplier including a polarity inversion function connected to the main taps of the P and Q channels, respectively, and a reference voltage. This method does not matter whether the algorithm of the automatic equalizer 2 is a ZF (zero facing) type or an ME (minimum error) type algorithm. Furthermore, in the ME type, since the two input signals of the equalizer are identified before equalization, the results of this identification can be used. FIG. 2 is a block diagram of a first embodiment of the conversion circuit 3. This is based on (a) above, and further inverts the signal X _p according to the polarity determination signal PL. That is, the polarity determination signal PL is applied to voltage comparators 7 and 7' each provided with a reference voltage E _s , and each output thereof is applied to an input of an exclusive OR circuit 8 . This output is applied to one input of another exclusive OR circuit 8' via a simple integration circuit RC. The output signal X _p of the automatic equalizer 2 is applied to the other input of this circuit 8'. This output and the other output X _q of the automatic equalizer 2 are
The signal is applied to the differential decoder 4. Signal CLK is a clock signal. Integrating circuit RC is for removing spikes and can be omitted without affecting basic operation. In such a circuit, the signal X _p can be further inverted according to the polarity determination signal PL to perform the operation (a) above. FIG. 3 is a block diagram of a second embodiment of the conversion circuit 3. This is based on (b) above. That is,
The polarity determination signal PL is applied to voltage comparators 7 and 7' each supplied with a reference voltage _Es , and each output is applied to exclusive OR circuits 8 and 8', respectively, via a simple integration circuit RC. It is being Input signals X _{p and} X _q are applied to the other inputs of the exclusive logic circuits 8 and 8', respectively, and the respective outputs are input to the input of the differential decoding circuit 4 as signals Y _p and Y _q . Given. With this configuration, the polarity of each of the P channel and Q channel is individually corrected. It operates correctly even when the P channel and Q channel are inverted at the same time. FIG. 4 is a block diagram of a third embodiment of the conversion circuit 3. This is based on (c) above. That is,
The two input signals X _p and X _q are passed through polarity inversion switches 9,
9' to the differential decoder 4. The polarity reversing switches 9, 9' are controlled by a polarity determination signal PL. FIG. 5 is a configuration diagram of a fourth embodiment of the conversion circuit 3. Of course, this example does not necessarily match the position of the conversion circuit shown in FIG. This is based on (d) above. That is, two signals
X _p and X _q are input to a differential decoder 4, and the output thereof is taken out via polarity inverting switches 9 and 9'.
The polarity inversion switch is controlled by the polarity determination signal PL. FIG. 6 is a block diagram of a fifth embodiment of the conversion circuit 3. In this example, ME
When using the above algorithm, two input signals can be identified before equalization, and the results of this identification can be obtained as polarity determination signals X _p ′, X _q ′.
The polarity determination signals X _p ′ and X _q ′ are used to invert the signal X _p . This example is based on (a) above. FIG. 7 is a block diagram of a sixth embodiment of the conversion circuit 3. In this example, as mentioned above, the polarity determination signals X _p ′,
In the case where X _q ' is obtained, the signal whose polarity has been inverted in the automatic equalizer 2 is itself individually corrected based on (b) above. Although the above example shows an example for an orthogonal binary amplitude modulation signal, the present invention can be similarly implemented for an orthogonal multilevel amplitude modulation signal because the polarity uncertainty for an orthogonal signal can be determined using two signals. be able to. As described above, according to the present invention, it is possible to obtain a circuit that can always perform correct differential decoding even when the polarity of a signal becomes uncertain inside an automatic equalizer.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram showing the configuration of a circuit according to an embodiment of the present invention. 2, 3, 4, 5, 6, and 7 are configuration diagrams of the first, second, third, fourth, fifth, and sixth embodiments of the conversion circuit. It is. DESCRIPTION OF SYMBOLS 1... Orthogonal multilevel amplitude demodulator, 2... Automatic equalizer, 3... Conversion circuit, 4... Differential decoder, 7,
7'... Voltage comparator, 8, 8', 8'', 8... Exclusive OR circuit.

Claims (1)

[Claims] 1. An orthogonal multilevel amplitude demodulator to which a received signal is input, an automatic equalizer to which the output signal of this demodulator is input, and a difference to which the output signal of this automatic equalizer is input. In a differential decoding device equipped with an automatic equalizer and a dynamic decoder, two carrier waves demodulated by carrier waves whose phases are orthogonal to each other based on a polarity determination signal detected by the automatic equalizer are used. (a) means for further inverting a predetermined one of the two signals; (b) means for individually modifying the signal which has undergone polarity reversal in the automatic equalizer; , (c) means for exchanging two signals at the input end of the differential decoder; and (d) means for exchanging two signals at the output end of the differential decoder. A differential decoding device with an automatic equalizer.