JPS6350666B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray tube oscilloscope, and more specifically, to a cathode ray tube oscilloscope, which displays multi-channel observed input signals time-divisionally and continuously on the horizontal axis of the cathode ray tube. It concerns oscilloscopes.

As a cathode ray tube oscilloscope for simultaneously observing multi-channel input signals, a device displaying a display as shown in FIG. 1, for example, has been widely used. The figure shows an example of 4 channels, in which CH1 to CH4 are displayed in four stages on the vertical axis. The frequency and level of these signals are read using markers that appear around the cathode ray tube, but in devices that do not display markers, they are read using a transparent cursor board (not shown) with grid-like markings. It is meant to be read. Although this type of conventional device is extremely convenient for observing multi-channel signals, it also has several drawbacks. In other words, in the correspondence between the input signal and the waveform displayed on the cathode ray tube, the input signal is A,
In a case where there are four types of changes: B, C, and D, for example, if you know that one of the signals D is a sine wave, CH2 of the displayed waveform is the signal D, and therefore , CH3 is signal A, CH4
It can be determined that CH1 is signal B and CH1 is signal C. However, in this case one of the channels is wasted and occupied for displaying the known signal. If there is no known signal, a circuit is required to clarify the correspondence between the input signal and the display channel, which inevitably complicates the device. In addition, it may be difficult to determine the positive or negative polarity of the input signal depending on the displayed waveform.Furthermore, since the display of each channel is arranged vertically, comparisons of mutual levels can be made. The problem is that it is difficult to do.

This invention was made to eliminate the above-mentioned drawbacks, and its purpose is to make it possible to display each channel signal in a time-divisional manner along the horizontal axis by adding a simple circuit to the conventional device. Our goal is to provide cathode ray tube oscilloscopes.

Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the accompanying drawings.

Referring to FIG. 2, this cathode ray tube oscilloscope consists of a device body 1 and a switchable input circuit 2 surrounded by a dotted line, and this device body 1 is constructed in the same manner as a conventional cathode ray tube oscilloscope. When the input circuit 2 is not connected to the main body 1 of this device, the displayed waveform is the same as that shown in Fig. 1 above, but when the input circuit 2 is connected, the signal waveform of each channel is shown in Fig. 3. They are arranged and displayed on the horizontal axis as shown.

Next, to explain the outline of the device main body 1, the terminal T
The observed signal input via the amplifier circuit 3 is appropriately amplified and applied to the Y-axis deflection plate of the cathode ray tube 5 via the Y-axis circuit 4, which is also generally referred to as the vertical axis. On the other hand, the output from the clock oscillator 6 is input to the amplifier circuit 8 via the switch 7, where it is converted into a sawtooth signal for time axis sweeping. This signal is applied to the X-axis deflection plate of the cathode ray tube 5 via the X-axis circuit 9, which is also called the horizontal axis, but the falling part of the sawtooth signal becomes an eyesore, so it is A blanking circuit 10 and the like are provided to prevent the display from being displayed. Furthermore, as shown in FIG. 1 above, it is provided with a staircase wave generation circuit 11 for displaying the signal waveforms of each channel in a vertically arranged manner. The display position of each channel is shifted in accordance with the output level of the staircase wave generation circuit 11, but the timing of this shift is determined by the control circuit 11.
The input signal channel change timing and the X-axis sweep timing are synchronized with each other. In addition, a marker circuit and other circuits (not shown) are provided, but since they have no direct relation to this invention, their explanations will be omitted. The input circuit 2 has a terminal T and a device main body 1.
The observed signal applied to the terminal T is sent to the amplifier circuit 3 of the device main body 1 while being switched for each channel at regular time intervals. It supplies timing pulses for sweeping to the amplifier circuit 8, and as shown in FIG. 4, it is composed of an input switching circuit 13 and a timing pulse generation circuit 14.

In this embodiment, the observed signal is assumed to consist of four channels CH1 to CH4, as in the example shown in FIG. It has T4. The channel signals CH1 to CH4 are applied to the corresponding terminals T1 to T4, respectively, and the channel signals CH1 to CH4 are applied to the corresponding terminals T1 to T4, respectively, and
output side terminal T via two resistors 15 to 18.
5 to T8 to the amplifier circuit 3.
Each of the circuits through which the CH1 to CH4 channel signals pass is provided with four switching circuits each of which is turned on and off by a signal from the timing pulse generating circuit 14. That is, in the circuit through which the channel signal CH1 passes, for example, the collector side of the switching transistor 19 is connected to the output terminal T5 side,
The emitter side is grounded. The base side is connected to a not circuit 21 via a resistor 20, for example.
To the input side of this knot circuit 21, a signal for on/off driving is applied from the timing pulse generation circuit 14 as described above. Although the power supply wiring is omitted in the above embodiment for convenience, it is assumed that a normal voltage is applied to each electrode of the transistor 19 and the transistor 19 is in an operating state. In this case, a current flows between the collector and emitter of the transistor 19, resulting in a short circuit state, so that no signal appears at the output terminal T5. Here, when an H level pulse is applied to the input side of the NOT circuit 21, an L level pulse is generated at the output side, and the resistor 2
0 to the base of the transistor 19. Therefore, the transistor 19 is turned off, and the channel signal CH1 applied to the input terminal T1 appears at the output terminal T5 via the resistor 15 during this time, and is sent to the amplifier circuit 3 of the main body 1 of the apparatus. Transistor 2 is also installed in each of the other three circuits through which channel signals CH2 to CH4 pass.
There are three switching circuits constructed in the same manner as above, including resistors 2, 25, and 28, resistors 23, 26, and 29, and knot circuits 24, 27, and 30.

The timing pulse generation circuit 14 includes four knot circuits 21, 24, and 24 of the input switching circuit 13.
27 and 30 sequentially, and the above 4.
For example, four flip-flop circuits (hereinafter referred to as "FF circuits") 31 to 34 and an AND circuit 35 for causing the four transistors 19, 22, 25, and 28 to perform switching operations;
An oscillator 36 for providing clock pulses to these F/F circuits, and an OR converting the four drive pulses from the F/F circuits into continuous pulses for X-axis sweeping and outputting them to the amplifier circuit 8 of the main body 1 of the device. circuit 37
etc.

In this embodiment, the F/F circuit is constituted by, for example, a JK type F/F circuit, and the clock input terminals CP1 to CP4 are connected to the oscillator 3.
Frequency variable clock pulses are applied in parallel from 6 to 6, so that there is no delay in the operation of each F/F circuit. Also, each K1 to K
A constant voltage of H level is applied to terminal 4, and F.
F circuit mutual output side terminal and input side terminal Q1 and J
2, Q2 and J3, Q3 and J4, etc. are connected by common wiring, and are connected to the above-mentioned note circuit 21, respectively.
It is also connected to the input sides of 24 and 27. In this case, the Q4 terminal of the final stage F.F circuit 34 is connected to the input side of the knot circuit 30 without a common wiring.
The three output terminals 2, 3, and 4 of the F/F circuits 32 to 34 are respectively connected to the input side of the AND circuit 35, and the output side of the AND circuit 35 is connected to the first stage F/F circuit 31. It is connected to the input side terminal J1 of. In this embodiment, the wiring for supplying drive pulses from each of the FF circuits to the knot circuit is also connected to the input side of the OR circuit 37. In this case, the other input side of the OR circuit 37 is grounded, and as described above, the four drive pulses are converted into one continuous pulse and output from the terminal T9.

Next, the operation of this device will be explained with reference to FIG. 5.

First, the oscillator 36 of the timing pulse generating circuit 14 sends out a clock pulse as shown in FIG. At this time, the first stage F・F circuit 3
Assuming that an H level signal happens to be input from the AND circuit 35 to J1 of 1, this F.
The F circuit 31 operates at the falling time t of the clock pulse.
1, and returns to the original state at the falling edge of the next clock pulse, t2. Therefore, an H level pulse as shown in (b) appears at one of the output terminals Q1. This pulse is the second
When applied to the input terminal J2 of the F.F circuit 32 in the second stage, the F.F circuit 32 starts operating, and an H level pulse appears at its output terminal Q2 as shown in FIG. Thereafter, the third F/F circuit 33 and the final stage F/F circuit 34 operate sequentially in the same manner, and their output terminals Q3 and Q4 receive H level signals as shown in D and E, respectively. A pulse appears.

At this time, the second stage or final stage F/F circuit 3
2, 33, 34 other output side terminals 2, 3,
Q4 has L as shown in G, J, and R, respectively.
A level pulse appears. These L level pulses are sequentially input to the AND circuit 35, but when one pulse is at L level, the other two are at H level, so three pulses are input at L level at the same time. There isn't. Therefore, during the period from t2 to t3 when these pulses are input, the output of the AND circuit 35 is at the L level as shown in . Referring again to FIG. 4, in this embodiment, the pulse appearing at 1 is not input to the AND circuit 35. Therefore, the L level pulse of 4 becomes H.
The period from t3 to t4 until the next 2 L level pulses are input.
Until then, each input side of the AND circuit 35 is kept at H level. As a result, an H level signal is output from the AND circuit 35 during this period, as shown in FIG. First stage F/F circuit 31
starts operating at the falling edge t1 of a clock pulse input when terminal J1 is at H level, and outputs an H level pulse as shown in (B) from terminal Q1. Now there are four F・
The operation of the F circuit completes its cycle. As can be seen from the above explanation and FIG.
Q4 output is sent out, but this Q4 output and the next Q
1 output, that is, from time t3 to t1, a one-step reset period is provided.
Therefore, the timing pulse sent from the OR circuit 37 to the main body 1 for X-axis sweeping is at the H level from time t1 to t3, as shown in F, and at the L level during the reset period from t3 to t1. . In this embodiment, during the L level,
Although the axis is not swept, this L level signal may be appropriately converted to display only the linear X axis indicating the reset period on the cathode ray tube, for example.

It is assumed that, in the input switching circuit 13, four channels of signals, such as those shown in (R) to (F), are inputted via terminals T1 to T4. In this case, when each of the transistors 19, 22, 25, and 28 making up the switching circuit is operating, these signals are short-circuited to the ground side via the collector and emitter of each transistor, and are not output to the device main body 1. . In this state, when the H level pulses of Q1 to Q4 as shown in B to E are input to the not circuits 21, 24, 27, and 30, L level pulses are output from these not circuits, respectively. added to the base of the corresponding transistor. Each transistor is turned off in sequence, and the input channel signals CH1 to CH4 are sent to the amplifier circuit 3 of the device main body 1 via the terminals T5 to T8 during the off period. In this case, if the switch 7 on the main body side is set to the B1, B2 side, the output of the staircase wave generation circuit 11 is cut off, and the X-axis is controlled from time t1 to t3 by the output from the OR circuit 37 shown in switch to normal single-stage sweep. As a result, each channel signal is displayed on the cathode ray tube 5 in a time-division manner and continuously as shown in y. Note that the portion without waveform display corresponds to the reset period and can be easily determined visually.

Although the above embodiment has been described for the case where the observed signal has four channels, it is clear that the gist of the present invention is not limited to the number of channels. Further, there is no particular need to provide a reset period after the final channel, and it can be set arbitrarily depending on which stage of the F/F circuit the input to the AND circuit 35 is taken from. Note that if a large number of channel signals are displayed on a single X-axis, each signal may become crowded and difficult to observe. In such a case, the output of the staircase wave generation circuit may be used in combination to make the X-axis multi-stage, and signals may be appropriately distributed to each stage for display.

As described above in detail, the cathode ray tube oscilloscope according to the present invention includes an input switching circuit that sequentially switches the observed input signals of multiple channels at a predetermined timing, and a switching operation that is performed by sending a driving pulse to the input switching circuit. The X-axis sweep is controlled by the drive pulses. As a result, there is one X on the cathode ray tube.
The waveforms of a plurality of channel signals are displayed on the axis, and a reset section in which no waveform is displayed appears between arbitrary channel signal waveforms that are adjacent to each other. Therefore, level comparison of each channel signal waveform and discrimination between positive and negative polarities are facilitated, and correspondence between input signal channels and displayed waveforms on the cathode ray tube can be easily determined due to the interposition of the reset section.

[Brief explanation of drawings]

FIG. 1 shows a waveform displayed on a cathode ray tube by a conventional device. 2 to 5 all relate to embodiments of the device according to the present invention, FIG. 2 is a block diagram thereof, FIG. 3 is a waveform displayed on a cathode ray tube, and FIG. 4 is a block diagram of a switching means. FIG. 5 is a timing chart. In the figure, 1 is the device body, 2 is a switching means, 5 is a cathode ray tube, 13 is an input switching circuit, 14 is a timing pulse generation circuit, 19, 22, 25, 28 are transistors, and 21, 24, 27, 30 are note circuits. , 31, 32, 33, and 34 are flip-flop circuits, 35 is an AND circuit, 36 is an oscillator, and 37 is an OR circuit.

Claims (1)

[Scope of Claims] 1. An input switching device comprising a switching circuit for each of a plurality of channels, which includes a semiconductor switching element and a gate circuit, and turns on and off a channel input signal via the switching element in response to a drive pulse input to the gate circuit. A cathode ray tube, the cathode ray tube having an input signal switching means comprising a circuit and a timing pulse generation circuit for controlling the operation of the input switching circuit, and displaying each multi-channel input signal on the cathode ray tube via the input signal switching means. In the oscilloscope, the timing pulse generation circuit includes a plurality of flip-flop circuits that have an oscillator and receives clock pulses from the oscillator and sequentially sends out the drive pulses to each gate circuit of the input switching circuit; an AND circuit which receives a pulse inversion signal and supplies a reset pulse to any one of the flip-flop circuits to provide a rest period after one cycle of sending out the drive pulses; and an AND circuit which converts each of the drive pulses into one continuous pulse and sweeps the cathode ray tube. 1. A cathode ray tube oscilloscope, comprising an OR circuit for sending out a trigger pulse, and a plurality of channel signals are displayed on the cathode ray tube in chronological order with respect to one time axis.