JPS6350717B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a display drive circuit for supplying image signals to matrix display pixels when displaying images such as television broadcasting in a matrix type image display device. The matrix type image display device described here is
The entire screen is composed of pixels subdivided in, for example, the X and Y directions, and each pixel displays an image by being distributed and applied with an image signal corresponding to the pixel by a selection circuit. There are various display materials such as liquid crystals, fluorescent materials, ferroelectric materials, etc., but since the present invention relates to the control method of the image sample circuit, the following explanation will use liquid crystals as an example if necessary. Give an explanation. FIG. 1 shows an example of an overall view of a television receiver using a matrix type image display device. 1 in the diagram
is a tuner section that selects the frequency of a predetermined channel from the radio wave signal input from the antenna. 2 is the circuit from the intermediate frequency amplifier to the video detection; 4 is the audio side intermediate frequency, detection, and output circuit; 3
is a video amplification circuit. 5 is a circuit that separates horizontal and vertical synchronizing signals from the video detection output, and outputs horizontal and vertical synchronizing signals to 6 and 7, respectively.
Reference numerals 8 and 9 indicate data sample circuits related to the present invention, which will be explained in detail later. Reference numeral 10 denotes a vertical scanning timing signal generation circuit for the matrix display section 11, which distributes the output of the data sample circuit 9 to each pixel of the matrix display section. An example of a specific circuit of the matrix display section 11 is shown in FIG. FIG. 2 shows an example of a circuit using a liquid crystal display material, and numeral 12 in the figure indicates the liquid crystal of each pixel.
Reference numeral 14 denotes a pixel selection transistor arranged for each pixel of the matrix. 13 is a capacitor inserted to supplement pixel capacity. FIG. 3 shows timing waveforms related to the data sampling method conventionally performed by blocks 8 and 9. In the figure, reference numeral 15 indicates a video signal waveform output from the video signal amplification circuit 3, which is generally a temporally serial analog image signal. 16 is a data sample pulse train for sampling the video signal 15 for each data line. On the signal waveform 15, each data sample point is indicated by a, b, c, d, and e. However, FIG. 3 is a simulated diagram, and the number of pulses, width, etc. are simplified. Incidentally, T ₁ indicates the horizontal period in the case of a television video signal, and T ₂ indicates the horizontal retrace period. FIG. 4 shows an example of a conventional specific circuit and waveforms of the data sample circuits 8 and 9. The circuit consists of a shift register, 17 is a transfer clock, 18 is a terminal for inputting register input timing data,
19 is a delay flip-flop. There are 16 portions of the gate control signals that switch the sample circuits of each data line. Now, input the video waveform shown in FIG. 3 15 to the terminal 20 in FIG. if,
The waveforms shown in FIG. 3 are produced at the outputs 24, 25, and 26 of each flip-flop 19, as shown in FIG. This waveform is connected to the control terminals of switch elements 28, 29, 30, and 31 to turn the switch elements on and off in sequence. Capacitor 1 arranged for each pixel of the liquid crystal matrix display section
3 sequentially holds the values of the image signal waveform 15 just before the switch element turns off, that is, the voltages at points a, b, c, . . . . All conventional matrix type image display drive circuits follow this type of system. The drawback of this conventional drive circuit is that it consumes a large amount of power. In general, power consumption largely depends on the characteristics of the elements used, but even if low power consumption complementary MOS integrated circuits are used, the amount of power consumed will be enormous, and when realizing portable televisions etc., the power consumption will account for a large proportion of the total weight of the power supply. We cannot guarantee a long battery life.
For example, when displaying on television, the number of pixels is
Approximately 500×500 is required, so approximately 500 stages of shift registers are required. On the other hand, one horizontal scanning time of a television signal is approximately 52μsec, excluding retrace time.
It is. Therefore, the frequency of the transfer clock 22 of the shift register 8 is =1×500/52×10 ^-6 ≒10 ⁶ Hz. It is known that the power consumption P of a complementary MOS integrated circuit is calculated from the gate capacitance, drain load capacitance C, power supply voltage V, and operating frequency. Assuming that P=CV ² V=15V and the gate and drain load capacitance per stage of shift register is 0.5PF, P=10 ⁶ ×0.5×10 ⁻¹² ×500×15 ² ≒56×10 ⁻³ W. It is an object of the present invention to eliminate such drawbacks of the conventional technology and to reduce the driving power in the shift register section to one-tenth or less. FIG. 5 is a diagram showing an embodiment of an image driving circuit according to the present invention. In the figure, reference numeral 37 denotes a flip-flop for constructing a shift register, and each stage is numbered F ₁ , F ₂ , F _{3 .} . . F _n as shown in the figure. Each output of the shift register is connected to a control terminal of a gate circuit 38 for switching the image signal applied to the image signal terminal 34, and sequentially switches the image signal. Terminal-
33 is a terminal for inputting register input timing data, and a waveform as shown in FIG. 3 is inputted thereto.
32 is the input terminal of the transfer clock and gate circuit-3
6 is logically ANDed and added to the flip-flop 37. The gate circuit 36 is composed of K gates and is named G ₁ , G ₂ . . . G _K as shown in the diagram. Gate circuit 36 selectively stops the clock pulse applied to shift register 37. As shown in Fig. 3, only one of the gate circuits 38 needs to be on at any time (no more than one is on at the same time), and as shown in Fig. 5, the shift register 37 is It is sufficient that the transfer clock pulse is supplied only to the flip-flops in the vicinity where the gate circuit 38 is on, and it is not necessary to supply the transfer clock pulse to all the flip-flops constituting the shift register 37 at all times. 3
5 is a second shift register which uses a terminal 40 as a data input terminal and sequentially sends signals input to this terminal to close any one of the gate circuits G ₁ , G ₂ . . . G _K. Numeral 39 is a frequency dividing circuit with a frequency division ratio of 1/n, which generates a clock for the second shift register 35. Let us calculate the power consumption when the number of stages of the shift register 37 is m, and it is divided into K blocks of n stages. If is the frequency applied to the terminal 32, and C is the sum of the gate capacitance and load capacitance per flip-flop stage, the power consumption P in the conventional circuit is as described above: P=CmV ^2In the circuit according to the present invention, the shift register 37
The power P ₁ consumed by P ₁ = CnV ² The power P ₂ consumed by the shift register 35 is:
Assuming that the flip-flop is the same as that of the shift register 37, P ₂ =/nCKV ² +P ₃ where P ₃ is the power consumed by charging and discharging the input capacitance of the gate circuit 36. Quite small compared to its capacity. If we ignore P ₃ for simplicity, η=P ₁ +P ₂ /P=n ² +K/mn (K=m/n) =n/m+1/n ² η is

It is minimum when [formula]. Therefore, when the shift register 37 has 500 stages, the power consumption is minimized by setting n=10 and K=50.
At this time, η becomes η=10/500+1/10 ² =0.03, and the power consumption can be reduced to 3% of the conventional value. In reality, due to power consumption such as the capacitance of the gate circuit-36, and an increase in the number of elements that make up the circuit, n
= around 20 to 50. FIG. 6 shows another image driving circuit according to the invention. In FIG. 6, instead of the shift register 35 in FIG. 5, a counter 40 and a decoder multiplexer 41 are used to select one of the gate circuits _G1 to _GK and supply a clock to each block of the closed shift register 37. . In this case, if binary counters are used for the counter 40 and the frequency divider 39, the power consumed in these parts will be less than the power of two flip-flops constituting the shift register 37.

[Formula] Since the power consumption of the decoder 41 becomes more complicated as K becomes larger, it is preferable to select K=10 to 20. Also,
When n=1 and K=m, shift register-3
7 can be omitted (the output of the decoder 41 is directly
Add to the control terminal of gate circuit-38. ) is likely to cause problems such as a timing shift of the counter 40. As described above, the present invention includes a plurality of pixels arranged in a matrix, a switching means for time-series sampling of an image signal using a sampling signal and supplying the sampled signal to each pixel column, and a switching means for supplying the sampling signal to the switching means. a shift register in which a plurality of stages are connected in series, and the plurality of stages are divided into a plurality of groups that are connected to each other in series; gate means for selectively supplying a transfer clock signal to the switch means, and the fixed time width includes at least the time during which the sampling signal is supplied to the switch means. Compared to the case where a transfer clock signal is constantly supplied to all of the shift registers, the supply of clocks to the shift registers is limited by the above-mentioned fixed time width, so power consumption can be significantly reduced. I can do it.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a television receiver using a matrix type image display device, Fig. 2 is a conventional drive circuit, Fig. 3 is a conventional timing waveform, Fig. 4 is a conventional data sample circuit, Fig. 5, FIG. 6 is a diagram showing a display driving circuit according to the present invention. DESCRIPTION OF SYMBOLS 11... Matrix type display body, 22... Transfer clock waveform, 23... Timing data waveform, 37... Shift register, 38... Gate circuit (analog),
36... Gate circuit, 41... Decoder, 40... Counter, 35... Shift register.

Claims (1)

[Claims] 1 a plurality of pixels arranged in a matrix; a switch means for sampling an image signal in time series using a sampling signal and supplying it to each pixel column;
supplying the sampling signal to the switching means;
A shift register in which a plurality of stages are connected in series, and the plurality of stages are divided into a plurality of groups that are successively connected to each other in the serial direction; gate means for supplying a transfer clock signal to the switch means, and the fixed time width includes at least a time during which the sampling signal is supplied to the switch means. Device.