JPS6350757B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay time control device suitable for application to testing equipment for logic elements such as semiconductor memories, and particularly provides a control device that can obtain an appropriate delay time in a short period of time. This is what I am trying to do.

Semiconductor memories are tested by applying various logic waveforms to multiple terminal pins. In this case, it is necessary that the logic waveforms applied to each terminal pin be maintained in a predetermined timing relationship. For this reason, a variable delay circuit is conventionally provided in the supply path of the logic waveform applied to each terminal pin, and control is performed so that the mutual timing is appropriate in the supply state of each logic waveform.

FIG. 1 shows a conventional delay time control device. In the figure, 111 is an output terminal of a logic waveform signal, 112 is a variable delay circuit, 113 is a driver, and output terminal 1
A logic waveform signal with a controlled delay amount is output to 14, and the logic waveform signal is input to one terminal pin of the device under test. 115 is a determination circuit that determines whether the timing of this logical waveform signal is advanced or delayed. This determination circuit 115 is composed of a level comparator 116 and a latch circuit 117. A logic waveform signal output from the driver 113 is inputted to one input terminal of the level comparator 116 through a selection switch 125. Here, the selection switch 125 is a switch that selects so that not only the output of the driver 113 but also the logical waveform signals supplied to other terminal pins can be supplied to the determination circuit 115. Therefore, the determination circuit 115 is shared by a plurality of transmission paths for logical waveform signals.

A voltage corresponding to, for example, 50% of the voltage when the logic waveform signal is at H logic is applied to the other input terminal of the level comparator 116 from the terminal 118, and the switch 12
The level of the logic waveform signal input through 5 is H.
The state of the output of comparator 116 is configured to invert when the logic 50% voltage is exceeded. That is, in this example, since the set voltage supplied to the input terminal 118 is applied to the inverting input terminal of the comparator 116, when the logic waveform is L logic, the output of the comparator 116 always outputs L logic. When the logic waveform output from the driver 113 exceeds 50% of the level at H logic, the output of the comparator 116 is inverted to H logic.

On the other hand, input terminal 119 is supplied with a reference clock having a reference phase. This reference clock is applied to clock input terminal C of latch circuit 117. This latch circuit 117 uses a D-type flip-flop, and its data input terminal D is connected to a comparator 1.
16 outputs are input. Therefore, if the output of comparator 116 is H logic when the reference clock is input, latch circuit 117 latches H logic and outputs H logic to output terminal 120. If the output of comparator 116 is L logic when the reference clock is input, L logic is output to output terminal 120. That is, when the output of the comparator 116 is L logic, the logical waveform signal 211 is in a leading phase with respect to the reference clock 212, as shown in FIG. 2, and when the output of the comparator 116 is H logic, it is lagging in phase. This progress,
Information representing the delayed phase is sent to the controller 121 that has a built-in computer, and from the controller 121 to the terminal 12.
2, a delay time correction signal is sent back. This delay time correction signal is output as a digital signal, and the correction signal is latched in the latch circuit 123. The correction signal latched by the latch circuit 123 is given to the DA converter 124, which converts the correction digital amount into an analog amount, supplies the analog amount to the variable delay circuit 112, and converts the amount of delay. I am trying to correct it.

In order to give the variable delay circuit 112 an appropriate delay time, if the phase is ahead based on the determination result of the determination circuit 115, the delay time is gradually controlled in the direction of increasing the delay time, and the determination circuit 115 determines that the delay time is gradually increased. When the result is reversed from, for example, L logic to H logic, the control is stopped, and the correction amount at that time is latched in the latch circuit 123. Therefore, it takes time to match the phase of the signal for one terminal pin, and this correction operation is performed for all terminal pins by conversion by the selection switch 125.
This method has the drawback that it takes a lot of time to set the phases of the logical waveform signal supply paths to all terminal pins to match. This setting changes the waveform of the logical signal to an RZ waveform.
This must be done every time the waveform is switched to the NRZ waveform, E-OR waveform, etc. Moreover, when testing logic circuit elements, the waveform is often switched, so the phase of the logic signal waveform for each terminal pin is changed every time the waveform is switched. There is an inconvenience that the test time is lengthened because of the need to perform matching.

An object of the present invention is to provide a delay time control device that can obtain an appropriate amount of delay in a short time.

FIG. 3 shows an embodiment of the invention. In FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant explanation thereof will be omitted. However, in this invention, a shift register is provided, and this shift register is used to determine the output state of H logic based on the determination result of the determination circuit. The variable delay circuit 112 is configured to be sequentially shifted and the contents of the shift register are sequentially DA-converted to control the variable delay circuit 112, and the amount of delay is given to the signal by the DA-converted value.
As a result, the contents of the shift register are latched by the latch circuit only when the phase of the signal becomes a delayed phase.

That is, 311 is a shift register. This example shows a case where an 8-bit shift register is used. Each output terminal Q ₁ to _{Q 8} of the shift register 311
The outputs of are supplied to input terminals D ₁ -D ₈ of latch circuit 123 through OR circuits 312a - 312h.
The outputs of the output terminals Qa-Qh of the latch circuit 123 are fed back to the input terminals _D1 - _D8 through OR circuits 312a-312h, respectively. At the same time, the output of each OR circuit 312a to 312h is transferred to the DA converter 1.
24 and is converted into an analog signal by the DA converter 124 to control the delay time of the variable delay circuit 112. Load terminal of shift register 311
An initialization signal is applied from the terminal 313 to the reset terminal R of the LOAD and latch circuit 123. This initialization signal causes the shift register 311 to
The latch circuit 123 is initialized to a state in which H logic is output only to output terminal _Q1 , and the latch circuit 123 outputs H logic to all output terminals.
The outputs of Qa to Qh are initialized to the L logic state.

An AND gate output of the determination result of the determination circuit 115 and a signal obtained by delaying the reference clock supplied from the terminal 119 by the delay circuit 314 is applied to the clock terminal C of the latch circuit 123. 315 is an AND circuit for performing this AND gate. The reference clock delayed by the delay circuit 314 is transferred to the delay circuit 31.
The signal is further delayed at step 6 and supplied to the clock terminal C of the shift register 311.

With this configuration, first the terminal 31
3, the shift register 311 is initialized to a state where the output terminal _Q1 becomes H logic. As explained earlier, this output terminal _Q1 is an MSB output, so this shift register 3
11 is set to "1, 0, 0, 0, 0, 0, 0, 0." This shift register 3
11 output "1, 0, 0, 0, 0, 0, 0, 0"
is input to the DA converter 124 through OR circuits 312a to 312h, and the value is subjected to DA conversion. Here, when the DA converter 124 is in the full scale input state "1, 1, 1, 1, 1, 1, 1, 1"
If the DA converter 124 has a characteristic of outputting 10V, the output voltage of the DA converter 124 will be 128/256×10V=5V in the initialization state. Therefore, the variable delay circuit 112
The delay time of is exactly at the midpoint of its variable range.
It is assumed that the delay time of the variable delay circuit 112 becomes shorter as the control voltage becomes higher.

For example, as shown in FIG. 4B, if the logical waveform signal 411 is ahead of the reference clock 212 in phase, the determination result of the determination circuit 115 will be L logic. Therefore, it is input to the terminal 119 and the delay circuit 314
The clock pulse delayed by AND gate 31
I can't pass 5. Therefore, the latch circuit 123 maintains all outputs at "0". On the other hand, the clock pulse is transmitted to the delay circuit 31.
6 to the clock terminal C of the shift register 311. By supplying this clock pulse, the state of the output is shifted, and the outputs of the output terminals Q1 to _Q8 become "0, _{1, 0} , 0, 0, 0, 0, 0". Therefore, the output of the DA converter 124 is also changed to a voltage corresponding to this digital value, and becomes 64/256×10V=2.5V. Since the control voltage of variable delay circuit 112 has decreased, its delay time becomes longer.
Therefore, the phase of the logic waveform signal is controlled to the delayed side, and as shown in FIG.
Suppose that the phase becomes more delayed. When the phase is delayed, the judgment result of the judgment circuit 115 becomes H logic,
As a result, AND circuit 315 is opened and a clock pulse is applied to clock terminal C of latch circuit 123. By supplying this clock pulse, the latch circuit 123 outputs "0, 1, 0, 0, 0, 0, 0,
0” is latched. When the latch circuit 123 completes the latch operation, a clock pulse is also supplied to the shift register 311 through the delay circuit 316 to shift the state of the shift register 311 by one more. Therefore, the output of the shift register 311 is “0,
0, 1, 0, 0, 0, 0, 0''. Since the latch circuit 123 has latched the previous state, the outputs of the AND circuits 312a to 312h are "0, 1,
1, 0, 0, 0, 0, 0''. For this reason, DA
The output of the converter 124 becomes 64+32/256×10V=3.75V, and the logic waveform signal 411 is controlled to lead phase again as shown in FIG. 4D.

As the logical waveform signal 411 advances in phase, the determination result of the determination circuit 115 becomes L logic again, and the AND circuit 315 is closed. Therefore, the next clock pulse is not supplied to latch circuit 123, and only shift register 311 is shifted.
Therefore, the output of the shift register 311 is "0, 0,
0, 1, 0, 0, 0, 0'', AND circuit 3
The outputs of 12a to 312h are “0, 1, 0, 1,
0, 0, 0, 0”. The DA converter 124 converts this digital value to 64+16/256×10V=3.125V, which converts the logic waveform signal 4 by the control voltage.
11 has a slightly advanced phase as shown in FIG. 4E.

In this way, the shift register 311
During this time, the latch circuit 123 latches H logic in the necessary bits, and the latched state is transmitted through the OR circuits 312a to 312h.
The logic waveform signal 4 is supplied to the DA converter 124, and as the shift of the shift register 311 progresses, the logic waveform signal 4
11 is gradually converged to the phase of reference clock 212.

As described above, according to the present invention, the proper delay state can be set by simply shifting the shift register 311 from MSB to LSB once, so that the proper state can be set while counting eight pulses. Therefore, the setting time can be significantly reduced.

In the above description, the shift register 311, the latch circuit 123, and the OR circuits 312a to 312h are provided for one logic waveform signal transmission path, but the shift register 311, latch circuit 312, and OR circuits 312a to 312h are provided for a plurality of signal transmission paths. circuit 12
3. The OR circuits 312a to 312h can also be shared. For that purpose, OR circuits 312a to 31
A switching circuit and a second latch circuit are provided between the 2h output and the DA converter 124, and the second latch circuit latches the latch result of the first latch circuit 123, and when the latch operation is completed, the switching circuit is closed. It may be configured to switch to perform a correction operation for the DA converter on another signal path. Therefore, a latch circuit is attached to each DA converter provided corresponding to each signal path, and the latch result of the latch circuit 123 explained in FIG. 3 can be latched by the latch circuit.

Moreover, although an example in which the present invention is applied to a circuit for matching the phase of logic waveforms of a semiconductor memory tester has been described above, it is easy to understand that the invention can be applied to other applications as well.

Further, in the above description, the case where the variable delay circuit 112 is inserted in the transmission path of the logical waveform signal is explained, but as another example, a variable delay circuit is inserted between the terminal 119 and the phase determination circuit 115, and this variable delay circuit It can also be configured to adjust the phase of the clock pulse. In that case, the driver 113
The phase of the signal output through the clock pulse is used as a reference to match the phase of the clock pulse.

[Brief explanation of the drawing]

FIG. 1 is a system diagram for explaining a conventional delay time control device, FIG. 2 is a waveform diagram for explaining its operation, FIG. 3 is a system diagram for explaining an embodiment of the present invention, and FIG. 4 is a system diagram for explaining a conventional delay time control device. is a waveform diagram for explaining the operation. 112: Variable delay circuit, 115: Judgment circuit, 1
24: DA converter, 123: latch circuit, 3
11: Means for increasing or decreasing the digital value supplied to the DA converter based on the determination result of the determination circuit.

Claims (1)

[Claims] 1. A variable delay circuit, a determination circuit that determines whether the delay time of this variable delay circuit is ahead or behind a reference value, a DA converter that outputs an analog value that determines the delay time of the variable delay circuit, and this DA converter. A delay time control device comprising: latch means for providing a digital value; and a shift register for gradually increasing or decreasing the digital value provided to the DA converter based on the judgment result of the judgment circuit.