JPS6351276B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to integrated circuit chips.

Conventional integrated circuit chips have a structure in which a memory array circuit section is surrounded by a logic circuit section, and the memory array circuit section cannot be directly accessed from input/output terminals of the chip.

In such conventional integrated circuit chips,
It is difficult to input proper test data and addresses to the memory array circuit, and the memory array circuit cannot be sufficiently tested. That is, since the logic circuit section surrounds the memory array circuit section, arbitrary data and addresses cannot be supplied to the memory array circuit section, making it extremely difficult to generate valid test data. .

These problems are becoming more and more prominent as the degree of integration of integrated circuit chips increases. As a means to solve this problem, a configuration has been considered in which the logic circuit section is bypassed. In such a configuration, in addition to the normal logic circuit section, bypassed data and the output of the logic circuit section are This requires a logic circuit for switching between the two, which poses problems in terms of layout design and performance of the integrated circuit chip.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide an integrated circuit chip that allows direct testing of memory-array circuitry.

In the integrated circuit chip of the present invention, a power supply pattern is formed so that only the voltage supplied to the logic circuit section can be changed, and the function of the logic circuit section is changed by changing the voltage, and the function of the logic circuit section is changed. It is constructed so that the circuit section can be directly inspected.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Integrated circuit chip 11 has a memory-array circuit section 12 and a logic circuit section 13. The memory array circuit section 12 has a write data line 14.
and address line 15 and read data line 1
6, and is connected to the logic circuit section 13 through the input terminal 17 and output terminal 18 of the integrated circuit chip 11.
is not directly connected to. Therefore, the memory array circuit section 12 cannot be directly accessed using the input terminal 17 and output terminal 18 of the integrated circuit chip 11.

In order to enable direct access to the memory array circuit section 12, in this embodiment, the external terminal 19 is
from the logic circuit section 13 via the power supply pattern 19'.
By changing the voltage applied to the chip, a voltage is created between the input of the memory array circuit 12 and the input terminal 17 of the chip, and between the output of the memory array circuit 12 and the output terminal 18 of the chip, as shown by the dashed line 20. electrical paths can be automatically created. Note that at this time, the memory array circuit section 1
A power supply pattern is formed so that the voltage applied to 2 does not change.

FIG. 2 shows an example in which the logic circuit section 13 is constructed of a current switching type circuit. In the figure, reference numeral 21 is a memory array circuit section, and shows an example of a 4.times.4 memory array circuit in which write data is 4 bits, read data is 4 bits, and address is 2 bits.

As shown in FIG. 3a, the NAND circuit 22 and AND circuit 23 used in FIG.
4 and a constant current source 36 (third
Figure a shows the case of 3 inputs). Negative value logic, low voltage level (e.g. -0.5V) is logic "1", high voltage level (e.g. GND level)
Assuming that corresponds to logic "0", the circuit shown in FIG.
It performs the actions represented by A, B, C, =... The base of the transistor 37 has a first reference potential VR1 (for example, -0.25V), and the base of the transistor 32
A second reference potential VR2 (for example -
1.1V), but the memory
When inspecting the array circuit section, transistor 3
Supplying a voltage (e.g., -0.75V) to the base of transistor 32 that is higher than the high voltage (supplied when input B or C is a logic 0) supplied to the base of transistor 32 causes transistor 32 to be in a normally on state. Therefore, the output performs only the operation represented by Z=A,=.

The exclusive OR circuit 24 of FIG. 2 includes transistors 33, 35 and 38, as shown in FIG. 3b.
It is composed of a resistor 34 and a constant current source 36. The relationship Z=AB and == exists between the two input signals A and B and the outputs Z and Z. When inspecting the memory array circuit section, if the second reference potential VR2 applied to the base of the transistor 33 is set to a high potential as in the case of FIG. 3a, the transistor 33 is always on. This results in outputs Z and Z=A and =A, respectively, with the output being determined only by the state of input A.

Similarly, the data selection circuit 25 in FIG.
As shown in FIG. c, it is composed of transistors 35, 39 and 40, a resistor 34, and a constant current source 36. Between inputs A, B and S and outputs Z and Z=SA+B and =+
There is a relationship. When inspecting the memory array circuit section, by setting the second reference potential VR2 applied to the base of the transistor 39 to a high potential, the outputs Z and Z become Z=A and =, respectively, so that simple operation can be performed. become.

Therefore, the logic circuit section of FIG. 2 consisting of the elements shown in FIG. 3a, FIG. 3b, and FIG. It turns into a simple element that propagates a single input state to its output. (In addition, in FIG. 2, power supply lines such as the first reference potential and the second reference potential that are supplied to each element are not shown.) With this function, the logic circuit section shown in FIG. A simple electrical path is formed as shown by the dashed line. As a result, input terminals 26, 27 and 28
By supplying write data, an address, and a write timing to the memory array circuit section 21 from the memory array circuit section 21, the output data of the memory array circuit section 21 can be observed via the output terminal 29. Therefore, the memory array circuit section can be directly tested from these input/output terminals.

As described above, the present invention has the advantage that the memory array circuit section can be directly tested by forming a power supply pattern so that only the voltage supplied to the logic circuit section can be changed.

[Brief explanation of the drawing]

1 and 2 are block diagrams and circuit diagrams respectively showing one embodiment of the present invention, and FIGS. 3a, 3b and 3c are diagrams for explaining the embodiment. In the figure, 11... integrated circuit chip, 12,
21... Memory array circuit section, 13... Logic circuit section, 14... Data input line, 15... Address input line, 16... Data output line, 17, 26, 2
7, 28... Input terminal, 18, 29... Output terminal, 19... Voltage input terminal, 22... NAND circuit, 23... AND circuit, 24... Exclusive OR circuit, 25... Data selection circuit, 31, 32, 3
3, 35, 37, 38, 39, 40...transistor, 34...resistor, 36...constant current source, VR1
...First reference potential, VR2...Second reference potential, A, B, C, S...Input, Z,...Output.

Claims (1)

[Scope of Claims] 1. A memory circuit section having a plurality of address input terminals, a data input terminal, and a data output terminal; a plurality of external terminals; each having a plurality of input terminals; It outputs a predetermined logic operation result based on all the input signals given to the input terminals of the input terminal, and when the second power supply voltage is supplied, the input signal given to a predetermined one of the plurality of input terminals is directly or logically outputted. A logic circuit section in which a plurality of logic elements that output inverted levels are connected in combination, and a logic circuit section to which a predetermined logic element is connected to the plurality of external terminals, address input terminals, data input terminals, and data output terminals; By supplying the second power supply voltage to the logic circuit section during inspection, the address signal and input data signal from the external terminal are directly transmitted to the address input terminal and the data input terminal, and the input data signal is directly transmitted from the data output terminal. An integrated circuit chip characterized in that a signal path for directly transmitting an output data signal to the external terminal is formed by the logic element in the logic circuit section.