JPS6351410B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logarithmic compression type level detection circuit that converts an input signal into a DC signal that is logarithmically proportional to the signal level.

Generally, in order to alleviate the limitations on signal dynamic range that occur in recording media such as magnetic tapes and other signal transmission paths, the signal dynamic range is compressed at the input side of the signal transmission path and expanded and restored at the output side. A so-called compander type noise reduction device is known. Such a compander-type noise reduction device consists of a variable transfer characteristic circuit including a voltage-controlled variable gain circuit that compresses and expands the input signal by changing its transfer characteristic according to the level and spectrum of the input signal, and this variable transfer characteristic circuit. and a level detection circuit for obtaining a control signal for controlling the transfer characteristic circuit.

By the way, in recent years, noise reduction devices for audio tape recorders have been used to obtain a greater noise reduction effect and to minimize the various disadvantages that occur along with this, such as noise modulation phenomenon and overshoot of signal rise. Therefore, a highly accurate voltage controlled variable gain circuit and level detection circuit with a wider dynamic range is required.

In view of these conventional circumstances, it is an object of the present invention to provide a level detection circuit that has desired rise and fall characteristics, has a wide dynamic range, and is highly accurate.

Here, FIG. 1 shows a full-wave rectification type linear detection circuit configured using an operational amplifier as an example of a conventional level detection circuit. In FIG. 1, the negative component of the AC input signal supplied to the input terminal 1 is inverted and taken out to the connection point a by the operational amplifier 3 and diodes 4 and 5, and the inverted output of this negative component is sent to the input resistor. 6 to an operational amplifier 7 , and the alternating current signal at the input terminal 1 is supplied to the operational amplifier 7 through another input resistor 8 . These resistors 6 and 8 and the operational amplifier 7 constitute a summing amplifier circuit, and the resistor 8 is connected to the second resistor 6.
By doubling the resistance value, an output signal obtained by full-wave rectification of the AC input signal of the input terminal 1 can be obtained at the connection point b. This rectified output signal is smoothed using a smoothing circuit 9 consisting of a resistor and a capacitor, and then outputted from the output terminal 2.

In this way, by correcting the rise characteristics (forward voltage drop) of the diodes 4, 5, etc. using the operational amplifier 3, etc., a somewhat wide dynamic range can be obtained. The limits are determined by the supply voltage and the circuit offset voltage, with typical values of approximately
It is 60dB.

For this reason, a level detection circuit that requires a dynamic range exceeding 60 dB uses a circuit configuration that applies exponential and logarithmic conversion. Generally 40~
When a dynamic range of 50 dB or more is required, it is more practical to use an exponential, logarithmic conversion, or logarithmic compression type level detection circuit.

Here, FIG. 2 shows a conventionally known logarithmic compression type level detection circuit 10. In this level detection circuit 10, a current source 21 representing an input signal source is connected to an input terminal 11. This input terminal 11 is connected to an inverting input terminal of an operational amplifier 14 via an absolute value circuit 20, which is a high-precision full-wave rectifier, and a terminal 13. The non-inverting input terminal of this operational amplifier 14 is grounded, and the output terminal is connected to a plurality of, for example, N diodes 1.
5, 15, . . . are connected to the inverting input terminal via series connection circuits. In addition, the operational amplifier 14
The output terminal of is connected to an integrating capacitor 17 via a diode 16, and the connection point between these diodes 16 and capacitor 17 is connected to the reference current source 1 via N-1 diodes 18, 18, .
9 is connected. Further, the output from the connection point between these diodes 18 and the reference current source 19 is taken out via the output terminal 12.

Next, FIG. 3 is a circuit diagram showing a specific example of the absolute value circuit 20. In FIG. 3, when a positive current, that is, a current in the direction of the solid arrow, flows through the input terminal 11, it is inverted by the operational amplifier 22 and the base of the transistor 24 is pulled to the negative side, so the transistor 24 is turned on. Current flows in the direction of the solid arrow. Therefore, one transistor 2 of the current inversion circuit (current mirror) 25
5a flows in the direction of the solid line arrow, and this also flows to the other transistor 25b, so that the output terminal 1
3, a current flows in the direction of the solid arrow. On the other hand, when a negative current, that is, a current in the direction of the dashed arrow, flows through the input terminal 11, the operational amplifier 2
2 becomes positive, and a current flows in the direction of the dashed arrow in one transistor 23a of the current inversion circuit 23, and this flows in the other transistor 23b, so that one transistor 25 of the current inversion circuit 25
A current flows in the direction of the dashed arrow, which is the same direction as the solid arrow. Therefore, at the output terminal 13,
Regardless of the positive or negative polarity of the input terminal 11, that is, the positive or reverse direction of the current, current flows in the same direction (in the direction of the solid line and broken line arrows).

Therefore, when the current flowing through the input signal source 21 in FIG. 2 is i _io (including positive and negative), the output current of the absolute value circuit 20 takes the absolute value |i _io
becomes ｜. Here, each diode 15, 16, 1
When the saturation current of 8 is I _S , the output voltage v of the operational amplifier 14 is as follows: v=N·V _T ln (|i _io |/I _S +1) . However, V _T =kT/q, where k is Boltzmann's constant, T is absolute temperature, and q is elementary charge.
Considering the transient state, assuming that the terminal voltage Vc of the capacitor 17 is fixed with respect to the instantaneous value,
The current i _d flowing through the diode 16 is: i _d = Is [exp (v-Vc/V _T )-1] = Is [(|i _io |/Is+1) ^N・exp(-Vc/V _T -1]... ...... If i _io is stationary, then _d = I _p
and _d = 1/T∫ ^T _p i _d dt = Is [1/Texp (−Vc/V _T )∫ ^T _p (|i _io |/Is) ^N d
t−1] = I _p ...... Vc that satisfies this is the steady solution of Vc. In other words, Vc is Vc=V _T [ln {1/T∫ ^T _p (|i _io |/Is+1) ^N dt} −ln (I _p /Is-1)] ...... The steady value of the output voltage V _p is V _p =Vc−V _T (N−1)ln(I _p /Is−1) =V _T [ln{1/T∫ ^T _p (|i _io |/Is+1) ^N dt} −Nln( I _p /Is−1)] ……… Actually, |i _io |, I _p ≫Is, so the approximate formula for V _p is V _p ≒V _T [ln{1/T∫ ^T _p (| i _io |/Is) ^N dt}−ln(I _p
/Is) ^N ] =V _T ln(| _io | _p ) ^N ...... However, | _io | ^N = 1/T∫ ^T _p | _{i io} | ^N dt.

Such a logarithmic compression type level detection circuit 10
obtains the N-th power mean of the absolute value of the input current i _io as the output. For example, when N=1, it is the average value of the input current, and when N=2, it is the effective value of the input current. By using such a level detection circuit 10, for example, dynamic range can be achieved.
Level detection of 80dB or more can be easily achieved.

However, in the case of a conventional noise reduction device using effective value detection, the ratio of rise to fall can only be maintained at about 4, and overshoot may occur when input has a fast rise.

Here, the transient response of the logarithmic compression type level detection circuit 10 will be considered. First, in the logarithmically compressed form,
Since the output is logarithmically compressed, the parameter to be actually evaluated as the detection output is not the output itself, but it is transformed into an index and a variable G(t) proportional to the input current (as a steady solution) is introduced. Here, G(t) is proportional to (i _io ^N ) ^1/N at t→∞, and is defined as follows.

G(t)=exp[V _p (t)/N・V _T ] ...... Here, V _p and Vc at time t are V _p (t) and V _T
(t). Furthermore, for the sake of simplicity, the input step is set to I _p , and when there is an input, there is a steady solution of V _p (t)=0 or G(t)=1.

First, to see the fall, as the input current i _io ,
The response to a step function of I _p when t<0 and 0 when t>0 is investigated. At this time, the steady solution at t<0 is, from the above and formula, Further, when t>0, i _d becomes substantially 0, and the integrating capacitor 17 (capacitance value is C) is I _p
This results in constant current discharge. Therefore, V _p (t)
is, V _p (t)=V _p (t) | _t=0 −I _p /Ct = −I _p /Ct ...... When G(t) is calculated from the above formula, G(t)=exp (-I _p /N・V _T・C・t) ...... This can be modeled using an equivalent circuit as shown in Figure 4, where the resistance R _p and capacitor C _p in the circuit are
takes the value R _p = 1/I _p ...... C _p = N・V _T・C ......, and the time constant τ is τ=R _p C _p = N・V _T・C/I _p ......

Next, in order to look at the rise characteristics, i _io =
0, t>0 and the response to an input current of i _io =I _p is analyzed. In this case, i _d at any time t>0
is i _d (t)≒Is・expv−Vc(t)/V _T ………, v(t) at t>0 is the same as the above formula, and furthermore, Vc(t) is expressed as V _p ( t),
The above formula becomes i _d (t)≒I _p ·exp [−V _p (t)/V _T ]. Next, the time change of V _p (t) is determined.

dV _p (t)/dt=i _d (t)-I _p /C = I _p /C [exp{-V _p (t)/V _T }-1]...
Substituting this V _p (t) with G(t), d[V _T lnG(t) ^N ]/dt=I _p /C[G(t) ^-N -1
] ……… is obtained, and when we organize this and find the time change of G(t), we get dG(t)/dt=I _p /N・V _T・C[G ^(1-N) −G( t)
] ...... This differential equation represents the rise characteristic.
This can be modeled with an equivalent circuit as shown in Figure 5, where the resistance R _p and capacitor C _p are R _p = 1/I _p ...... C _p = V _T C ...... Nonlinear circuit 29 corresponds to the input g(t), and obtains the output G(t) as follows: G(t)=[g(t)] ^1/N . . .

Incidentally, the time constant required for an audio noise reduction device configured using such a level detection circuit 10 is several times the time constant at the time of rise (at the time of attack).
It is as short as 100 μsec to several msec, and as long as several tens of msec to several hundred msec at the time of falling (recovery), with a difference of about several hundred times. Here, when the above-mentioned N is 1, the rising and falling are equal, and the larger N is, the faster the rising is. In order to prevent overshoot from occurring when an input with a fast rise is applied, it is necessary to make the rise time constant fast. However, when N is set large in order to achieve an opening several hundred times as described above, the following drawbacks occur.

That is, first, in response to the increase in N, the number of PN junctions in the series circuit of diodes 15, 15, ..., 18, 18, ... increases, and the voltage drop steadily increases, making it difficult to operate at a low power supply voltage. Become. in this case,
It is conceivable to use an amplifier with a gain of N to enable low power supply voltage operation without relying on a series circuit of a PN junction, but this would complicate the circuit configuration. Next, the conversion coefficient of the output voltage changes corresponding to N as shown in the above equation. In other words, from the formula, V _p ≒N・V _T ln [(|i _io |/Io) ^N ] ^1/N ...... This output can be used to control a log-linear voltage controlled variable gain circuit proportionally or inversely proportionally. In order to control this, a 1/N attenuator is required.

Hereinafter, preferred embodiments of the present invention will be described.
This will be explained with reference to the drawings.

FIG. 6 is a circuit diagram showing a level detection circuit 30 as a first embodiment of the present invention. In this FIG. 6, the current source 21 which is the input signal source is
An input current i _io is supplied to the input terminal 11 . Input terminal 11 is connected to an inverting input terminal of operational amplifier 31 via absolute value circuit 20 and terminal 13 . The non-inverting input terminal of the operational amplifier 31 is grounded, and the output voltage v ₁ is fed back to the inverting input terminal via the logarithmic conversion diode 32. Also,
The output voltage v ₁ of the operational amplifier 31 is
is applied to the non-inverting input terminal of , and taken out as voltage v ₂ from the output terminal.

Next, the output terminal of the operational amplifier 33 is connected to an integrating capacitor 35 via a diode 34, and these diodes 34 and capacitors 3
At the connection point with 5, there is a current source 36 that flows a reference current I _p .
is connected. Output voltage of capacitor 35
Vc is sent via an operational amplifier 40 as a voltage follower to a series circuit of a diode 41 and a current source 42 that flows a reference current I _p , and is connected to the connection point between these diodes 41 and the reference current source 42. An output voltage V _p is taken out from the output terminal 12 .

Further, as a feature of the present invention, a voltage dividing circuit 46 is provided to divide the voltage between the output voltage Vc of the integrating capacitor 35 and the output voltage v ₂ of the operational amplifier 33, and the divided voltage output from the voltage dividing circuit 46 is Operational amplifier 33
It is fed back to the inverting input terminal of. In this case, since it is not preferable to take out the terminal voltage of the integrating capacitor 35 directly, it is taken out via the voltage follower operational amplifier 40 and supplied to the voltage dividing resistor 48 of the voltage dividing circuit 46 . Further, the output voltage v ₂ of the operational amplifier 33 is level-shifted to voltage v ₃ via the diode 43, and is supplied to the voltage dividing resistor 47 of the voltage dividing circuit 46 via the operational amplifier 45 as a voltage follower. . Diode 43 compensates for the steady-state value of the voltage drop caused by diode 34. The resistance value of the resistor 47 of this voltage dividing circuit 46 is set to N-1 times that of the resistor 48, and the divided output voltage _v4 at the connection point of these resistors 47 and 48 has a 1/N difference between the input voltages. and 1/(N-1). Note that at the connection point between the diode 43 and the operational amplifier 45, there is a current source 4 that flows the reference current I _p .
4 are connected.

In the level detection circuit 30 having such a configuration, the voltage v ₁ logarithmically converted by the diode 32 and the operational amplifier 31 is v ₁ =V _T ln (|i _io |/Is+1) . However, V _T is as explained in the above formula. Now consider a transient state and assume that the output voltage V _p is fixed relative to the instantaneous value. Voltage divider circuit 4
Since the divided output voltage v ₄ of No. 6 is equal to the voltage v ₁ at the input of the non-inverting terminal of the operational amplifier 33, the voltage v ₃ applied to the voltage dividing resistor 47 via the voltage follower is
is given by v ₃ =N·v ₁ −V _p (N−1) = N·V _T ln(|i _io |/Is+1)−Vc(N−1) . Therefore, the output voltage v ₂ of the operational amplifier 33 is: v ₂ =N・V _T・ln (|i _io |/Is+1) +V _T・ln (I _p /Is+1) − Vc (N−1) …… ...〓〓, and the instantaneous current i _d flowing through the diode 34 is i _d = Is [exp (v ₂ - Vc/V _T )-1] = Is [(|i _io |/Is+1) ^N (Io/Is +1 ) exp(−N・Vc/V _T )−1〕 ………〓〓. If the input current i _io is stationary, then _d = I _p , i _d = 1/T∫ ^T _p i _d dt = Is [1/T(Io/Is+1)・exp(-N・Vc／V
_T ∫ ^T _p (｜i _io |/Is +1) ^N dt−1〕=I _p ………〓〓 Vc that satisfies this is the steady solution of Vc, and Vc=V _T /N・ln[1/ T∫ ^T _p (｜i _io ｜/Is+1) ^N
dt……〓〓 Calculating the output voltage V _p , V _p =Vc−V _T ln(I _p /Is+1) =V _T /Nln [1/T∫ ^T _p (|i _io |/Is+1) ^N dt
] −Vt・ln(I _p /Is+1) ………〓〓 is obtained. In fact, |i _io |, I _p ≫Is, so
Finding an approximate value, V _p ≒V _T /Nln[1/T∫ ^T _p (|i _io |/Is) ^N dt]−V _T・
ln(I _p /Is) =V _T ln[1/T∫ ^T _p (｜i _io |/I _p ) ^N dt] ^1/N ………
〓〓 Here, 1/T∫ ^T _p (｜i _io ｜/I _p ) ^N dt≡ (｜i _io ｜/I _p ) ^N
......, we get V _p ≒V _T ln [(|i _io |/I _p ) ^N ] ^1/N ......

In the logarithmic compression type level detection circuit 30 according to the present invention, the conversion coefficient does not depend on changes in N. Therefore, the variable to be introduced as G(t) is defined as G(t)=exp[V _p (t)/Vt] .

First, to see the fall, input current i _io is t<0
Analyze the response when I _p is 0 with t>0. t<
The stationary solution at 0 is V _p (t)=0, and t>0
Then, since the integrating capacitor 35 releases a constant current at the reference current I _p , at t>0, V _p (t)=-I _p /Ct......〓〓 G(t)=exp(-I _p /V _T・Ct) ......〓〓 is obtained.

Next, as a rising edge, the response to input current i _io is 0 when t<0 and I _p when t>0 is analyzed. t>0
i _d at any time is i _d (t)≒Is.expv ₂ (t)−Vc(t)/V _T ………〓
〓 is. v ₂ (t) is approximated by the above formula, v ₂ (t)≒(N+1)ln(I _p /Is)−Vc(t) ^(N-1
) ...〓〓 And further, if we express Vc (t) by V _p (t), then
v ₂ (t)−Vc(t) is v ₂ (t)−Vc(t)=V _T ln(I _p /Is)−NV _p (t) ……〓〓. Therefore, i _d (t) can be expressed as follows.

i _d (t)≒I _p・exp(−N・V _p (t)/V _T ………〓
〓 Also, when calculating the time change of V _p (t), dV _p (t) / dt = i _d (t) - I _p /C = I _p /C [exp{-N・V _p (t) / V _T }-1] ………〓〓 Then, replacing V _p (t) with G(t), d[V _T lnG(t)]/dt=I _p /C[G(t) ^{- N} -1
] ………〓〓 Organizing this and finding the time change of G(t), we get dG(t)/dt=I _p /V _T C[G(t) ^(1-N) −G(t
)] ………〓〓 is obtained.

Here, when comparing the present invention and the conventional example, the above expression 〓 〓 corresponds to the above expression, and the above 〓 〓 expression corresponds to the above expression. Therefore, it can be seen that if the capacitance value of the integrating capacitor 35 of the present invention is multiplied by N, the circuit becomes completely equivalent to the conventional circuit.

Next, FIG. 7 is a circuit diagram showing a level detection circuit 60 as a second embodiment of the present invention. In FIG. 7, parts corresponding to those in the first embodiment shown in FIG. 6 are given the same reference numerals and their explanations will be omitted.

In the second embodiment shown in FIG. 7, a transistor 50,
The structure of the emitter follower according to No. 55 is used to simplify the circuit. Further, the non-inverting input terminal of the operational amplifier 31 is connected to a diode 53 and a constant current source 5.
It is grounded via level shifting means consisting of 4 and 4. Furthermore, a resistor 52 is inserted and connected between the diode 34 and the integrating capacitor 35 so that the rise curve approaches a normal first-order time constant curve. That is, this resistor 52 has the function of preventing the charging current to the integrating capacitor 35 from becoming particularly steep due to a particularly steep initial rise when the value of N is set to a large value. This is important when N is large. In addition,
Transistor 51 in FIG. 7 is used in place of diode 41 in FIG. 6.

Next, instead of the resistive voltage dividing circuit 46 described above, a resistive voltage dividing circuit 146 as shown in FIG. 8, for example, can be used. In this resistance voltage dividing circuit 146, the connection point of the voltage dividing resistors 47 and 48 is grounded via a resistor 49, and by adding this resistor 49, the conversion coefficient of the output can be arbitrarily set.

As is clear from the above description, according to the level detection circuit according to the present invention, even if the N is set to a large value, the voltage reduction characteristics of the circuit will not deteriorate and the circuit will not become complicated. In particular, when N>3, great effects can be obtained compared to the conventional configuration. In addition, since the conversion coefficient of the output voltage is not affected by changes in N, a 1/N attenuation circuit is not required.
For example, connection with a log-linear voltage controlled variable gain circuit can be more easily made. Furthermore, since the conversion coefficient of the output voltage is not affected by N,
It becomes possible to change N from the outside and control it according to the level. This enables a configuration in which the response time constant is controlled depending on the input level, for example.

Note that the present invention is not limited to the above-mentioned embodiments, and various changes can be made without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a full-wave rectification type level detection circuit, FIG. 2 is a circuit diagram showing an example of a conventional logarithmic compression type level detection circuit, and FIG. 3 is a specific example of the absolute value circuit 20. The circuit diagrams illustrating examples, FIG. 4 and FIG. 5, are equivalent circuit diagrams modeling the falling and rising characteristics of the circuit of FIG. 2, respectively. FIG. 6 is a circuit diagram showing a first embodiment of the present invention. FIG. 7 is a circuit diagram showing a second embodiment of the present invention. FIG. 8 is a circuit diagram showing another specific example of the resistive voltage divider circuit. 32... Diode for logarithmic conversion, 33... Operational amplifier, 34... Diode as a PN junction element, 35... Integrating capacitor, 46... Resistance voltage divider circuit.

Claims (1)

[Claims] 1 means for logarithmically converting an input signal, an operational amplifier to which this logarithmically converted voltage is applied to a non-inverting input terminal, a PN junction element whose one end is connected to the output terminal of this operational amplifier, and this PN junction element. an integrating means connected to the other end, means for resistively dividing the output voltage of the integrating means and the output voltage of the operational amplifier, and means for feeding back the output of the resistive dividing means to the inverting input terminal of the operational amplifier. A logarithmic compression type level detection circuit comprising: