JPS6352464B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated device, and more particularly to a semiconductor integrated device suitable for increasing withstand voltage.

In recent years, as the applications of semiconductor integrated devices (hereinafter referred to as ICs) have expanded, there has been a demand for high voltage ICs.
In particular, there is a strong demand for interface elements between logic ICs, such as μ-controllers, and power elements for commercial voltage, and electronic switches for telephone exchanges that replace cross-operated switches.

When expressing such a high voltage IC,
It is necessary to have means for increasing the withstand voltage of the elements themselves incorporated in ICs, and means for insulating and separating and integrating the elements.
Various methods have been proposed for each.
When aiming to achieve a high breakdown voltage of 100V or more, a field plate is suitable for the former, and a dielectric separation method is suitable for the latter, not only from the standpoint of increasing the breakdown voltage but also from the standpoint of high integration and mass production.

From this point of view, conventional methods such as the one shown in Figure 1 have been used.
An IC structure has been proposed and put into practical use.

In the figure, 1 is a dielectric insulation isolation substrate;
From the polycrystalline silicon support region 2, the plurality of single crystal silicon island regions 3a to 3c, and the insulating isolation films 4a to 4c, which are first insulating films, for insulating the island regions from each other and between the support region and each island region. It is configured. In each of the island regions 3a to 3c, impurities are diffused into predetermined locations using known photolithography technology or selective diffusion technology, and active elements such as transistors and thyristors or passive elements such as resistors are incorporated.

The figure shows an example in which thyristors are incorporated in the island region 3a using four layers p _E , p _B , n _B , and n _E.

Here, each single-crystal island region 3a-3c is buried in the polycrystalline silicon support region via insulating separation films 4a-4c so as to be exposed on one main surface of support region 2.

Furthermore, the single crystal silicon island region 3a includes an _nB layer which is a first layer of the first conductivity type exposed on the main surface of the single crystal silicon island region 3a, and a single crystal silicon island region 3a adjacent to the _nB layer. The first pn junction formed between the n ⁺ layer for channel cut, which is the second layer with high impurity concentration of the first conductivity type exposed on the main surface of the monocrystalline silicon island region 3a, and the _nB layer A second pn layer is formed between the _pE layer, which is the third layer of the second conductivity type, formed within the _nB layer so as to terminate on the main surface of the nB layer, and the _nB layer.
A fourth conductive layer of the second conductivity type formed in the _nB layer such that the junction terminates on the main surface of the single crystal silicon island region 3a.
The p _B layer and the third layer formed between the p _B layer
It has an _nE layer which is a fifth layer of the first conductivity type formed within the _pB layer so that the pn junction terminates at the main surface of the single crystal silicon island region 3a.

On the upper main surface of the substrate 1, a second insulating film 5 such as a silicon oxide film or a silicon nitride film, a surface stabilizing film,
Wiring lines 6a and 6b, which are provided as an insulating film and make ohmic contact with the _pE layer and the _nE layer through openings provided in the second insulating film 5, extend over the second insulating film 5. . In the island region 3a, wirings 6a, 6b
An N ^{+ layer is provided for the channel cut in the lower part where the N +} layer extends.

When the wiring 6a or 6b has a negative high potential with respect to the island region 3a, a channel is induced on the surface of the island region 3a due to the electric field effect, and this is caused by the insulating separation film 4a.
When connected to a channel generated along the channel, the current generated in the channel increases the leakage current of the device, that is, reduces the withstand voltage. Therefore, this channel-cutting n ⁺ layer, which cuts the channel and reduces leakage current, is essential for high-voltage IC elements.

Here, the wiring 6a is connected to the single crystal silicon island region 3.
A is in ohmic contact with the _pE layer on the main surface of the single crystal silicon island region 3a, and a second
The layer is formed so as to extend over the _pE layer and onto the _nB layer through the insulating film 5, and partially extend over the _nB layer and onto the channel cut n ⁺ layer. . Also,
The wiring 6b is in ohmic contact with the nE layer in the _pB layer on the main surface of the single crystal silicon island region 3a, and is in ohmic contact with _{the nE} layer on the main surface of the single crystal silicon island region 3a.
n _B over the n _E layer and p _B layer through the insulating film 5 of
The layer is formed so as to extend over the channel cut layer and partially extend over the n _B layer and onto the channel cut n ⁺ layer.

In order for the wiring 6a, 6b to function as a field plate, the wiring 6a, 6b on the n _B layer is
By reducing the thickness of the second insulating film 5 underneath, the depletion layer formed in the n _B layer and the p _B layer in the voltage blocking state can easily extend laterally along the main surface. The electric field concentration at the exposed edge of the P _-O junction shown in (c) and the corner of the p-n junction shown in (d) is alleviated.

However, although the n ⁺ layer for channel cutting is highly effective in reducing leakage current, the thickness of the second insulating film becomes thinner at the end mounting base exposed to the main surface shown in A and B. It was found that increasing the withstand voltage becomes difficult because it causes avalanche breakdown due to electric field concentration.

An object of the present invention is to overcome the drawbacks of the prior art and provide a dielectrically isolated semiconductor integrated device that can achieve high breakdown voltage.

A feature of the present invention that achieves the above object is that a plurality of single crystal island regions are embedded in a polycrystalline semiconductor support region with a first insulating film in between so as to be exposed on one main surface of the support region. , each single crystal island region includes a first layer of a first conductivity type exposed on the main surface of the single crystal island region, and a first layer adjacent to the first layer and exposed on the main surface of the single crystal island region. A second layer formed within the first layer such that a p-n junction formed between a conductive type high impurity concentration second layer and the first layer terminates at the main surface of the single crystal island region. a third layer of a conductivity type, and is in ohmic contact with the third layer on the main surface of the single crystal island region, and has a second insulating film on the main surface of the single crystal island region. extending over the first layer over the third layer;
In the semiconductor integrated device, the second insulating film includes a portion of the wiring that extends over the second layer beyond the first layer. is thicker than the thickness of the portion on the third layer, and the stepped portion is present on the first layer.

The semiconductor integrated device of the present invention will be explained below based on the embodiments shown in the drawings.

FIG. 2 shows one embodiment of the present invention.
The same reference numerals as in the figures indicate the same or equivalent parts.

The difference from FIG. 1 is that the second insulating film ⁵ includes a _p It is thicker than the thickness of the portion 5a on the _pB layer, which is the fourth layer, and the stepped portion exists on the _nB layer, which is the first layer.

In addition, in Figure 2, for channel cut
The n ⁺ layer is provided along the first insulating film 4a on the side wall of the island, and the n ⁺ layer for channel cut is provided on the first insulating film 4a.
The impurity concentration increases as the impurity concentration approaches the insulating film and toward the island sidewall.

The depth of p _E layer and p _B layer is 5 μm, and the specific resistance of n _B layer is 20
It is Ω・cm. The depth of the _nE layer is 3 μm, but the depth of the channel cut n ⁺ layer is 9 μm. The thickness of the SiO ₂ layer 5a under the wiring portion functioning as a field plate is 1.2 μm, and the thickness of the SiO ₂ film 5b on the channel cut n ⁺ layer is 3.0 μm.

In this embodiment, the thickness of the second insulating film 5a on the _pE layer and _pB layer under the wiring portion functioning as a field plate is the same as the thickness of the insulating film 5b on the n ⁺ layer for channel cut. Since it is relatively thinner than the first pn junction formed by the _pE and _nB layers, and the second pn junction formed by the _pB and _nB layers near the terminal end to the main surface. Electric field concentration can be alleviated. Further, since the thickness of the insulating film 5b on the channel cut n ⁺ layer can be increased, electric field concentration near the exposed end portion of the channel cut n ⁺ layer to the main surface can be alleviated. Furthermore, in this example, since the stepped portion exists on the _nB layer, a small electric field concentration also occurs in this portion, and the first
The electric field concentration near the end of the p-n junction, the second p ^- n junction, and the exposed end of the main surface of the channel-cut _n Therefore, it becomes possible to obtain a semiconductor integrated device with a high breakdown voltage.

Furthermore, in this embodiment, the difference in thickness between the second insulating film Sb on the n ⁺ layer for channel cut and the second insulating film 5a under the wiring portion functioning as a field plate is can be reduced. In other words, the concentration gradient on the main surface of the channel-cut n ⁺ layer 5b is relaxed by a factor of sin θ (<1) compared to the conventional structure shown in FIG. will be correspondingly relaxed. Therefore, if the thickness 5b of the second insulating film interposed between the wirings 6a and 6b extending across the n ⁺ layer for channel cut and this n ⁺ layer is the same as that of the conventional structure, Since a higher breakdown voltage can be obtained, and if the same breakdown voltage as the conventional structure is to be achieved, this second insulating film 5b can be made thinner.
It is possible to reduce the level difference between the two lines and prevent the wiring from breaking.

FIG. 3 shows a manufacturing process for the embodiment shown in FIG.

First, as shown in FIG. 3a, an n-type single crystal silicon substrate 31 having a desired resistivity is prepared. The thickness of this silicon substrate 31 is preferably a thickness that can withstand handling, for example, in the case of a 50 mmφ substrate, about 300 μm. Further, it is preferable that the plane orientation is <100>. Next, a silicon oxide film 3 of about 1 μm is formed on the silicon substrate 31 by thermal oxidation at a temperature of about 1100°C.
After that, a separation groove 33 of a predetermined depth (for example, 60 μm) is formed using known photoetching technology and anisotropic etching technology. Then, antimony is diffused into this separation groove 33 to form an n ⁺ region 34 for channel cut. The impurity concentration of the n ⁺ region as a channel stopper is mainly determined by the resistivity of the silicon substrate 31 and the magnitude of the voltage applied to the wiring of the high voltage circuit. In general, values that are not reversed due to the electric field effect due to the potential of the wiring, for example,
It is preferably about 10 ¹⁸ atoms/cm ² .

Next, for the separation groove 33 and the channel cut
1100℃ on the surface including the n ⁺ region 34 as shown in Figure 3b.
An insulating silicon oxide film 32 having a thickness of about 1.7 μm is formed by a thermal oxidation method of about 1.5 μm. Next, as shown in FIG. 3c, a polycrystalline silicon layer 35 is formed which is thicker than the depth of 60 μm of the separation groove 33 and is durable for handling. This polycrystalline silicon layer 35 is made of, for example, hydrogen (H ₂ ) gas containing trichlorosilane (SiHCl ₃ ) raw material.
It can be formed by gas phase chemical reaction at 1100-1200°C. Next, if the silicon substrate 31 is removed by polishing or etching until it reaches the position shown by the broken line in FIG. A dielectric insulation isolation substrate 37 for a semiconductor integrated device having a plurality of isolated single crystal islands (island regions) 36 on one main surface is obtained. At this time, the isolation region consisting of the polycrystalline silicon (supporting region) 35 and silicon oxide film (insulating film) 32 exposed on the upper main surface of the dielectric isolation substrate 37 corresponds to the bottom of the V-shaped isolation groove 33. The spacing can be very narrow, thus greatly increasing the degree of integration.
As shown in FIG. 3e, functional elements 36 such as thyristors, transistors, diodes, and resistors are formed on the monocrystalline islands 36 of the dielectric isolation substrate 37 thus formed, and aluminum wiring 3
By carrying out step 9, the semiconductor integrated device shown in FIG. 2 can be obtained.

As described above, the channel cut semiconductor layer 34
can be formed when making the dielectric isolation isolation substrate, and the second
Since it is not necessary to form an opening in the insulating film, the second insulating film on the channel cut semiconductor layer 34 is flat, and therefore, no break in the wiring occurs in the exposed part of this semiconductor layer. .

Further, the semiconductor layer for channel cutting can be formed before forming the insulating separation film. Therefore, compared to the conventional structure, the steps from the insulation isolation formation process to the _nE layer formation process (in the conventional structure, the n ⁺ layer for channel cut is formed at the same time as the _nE layer formation process to simplify the process).
Since the impurities forming the channel gut semiconductor layer are further diffused by the amount of heat treatment in the series of processes leading up to this step, a gentler concentration gradient can be automatically obtained. In other words, a gentler concentration gradient can be obtained than in the same process, and electric field concentration can be further alleviated, so the difference in thickness between the insulating film on the semiconductor layer for channel cutting and the insulating film under the wiring part that functions as a field blade can be further reduced. Can be reduced.

In the embodiment shown in FIG. 2, the breakdown voltage of the lateral thyristor in both forward and reverse directions was 410 to 450V. Avalanche breakdown development was observed, and the leakage current at applied voltages below the breakdown voltage was as small as 10 ^-5 A or less. Even when the polycrystalline potential is changed, no increase or decrease in leakage current is observed, and it is clear that the n ⁺ layer for channel cutting is functioning sufficiently. Moreover, the so-called walk-out phenomenon, in which the withstand voltage increases with time after voltage is applied between the anode and cathode, is not observed. Therefore, it is presumed that the breakdown voltage is not controlled by the surface of the n ⁺ layer for channel cutting or the surface of the p layer, but is determined by avalanche breakdown at the junction corner within the Si pulse.

By the way, for channel cut in this example
When the insulating film 5b on the n ⁺ layer is made 25 μm or less, the withstand voltage is
At low voltages below 300V, a significant walkout phenomenon is observed. On the other hand, even if the thickness is 3.5 μm or more, the withstand voltage is the same. Note that if the thickness of the insulating film 5a under the wiring, which functions as a field plate, is 1.5 μm or more, the withstand voltage will be reduced to 280V or less. From these facts, it is clear that the wiring as a field plate and the n ⁺ layer for channel cut function properly and sufficiently in this example described above.
Further, when the thickness of the Al wirings 6a and 6b is 2.5 μm, no disconnection occurs.

On the other hand, in the device with the conventional structure shown in Figure 1, when the oxide film thickness, junction depth, and substrate concentration are the same as in Figure 2, the breakdown voltage of the lateral thyristor in both forward and reverse directions is
It is 290 to 320V and a clear walkout phenomenon is observed. There is a tendency for the withstand voltage to increase as the insulating film 5b on the channel cut n ⁺ layer is increased, but approximately
Even with a thickness of about 4.0 μm, a breakdown voltage of 400 V or more could not be obtained. In addition, in this case, even if the thickness of the Al wiring was set to 3.2 μm, disconnections were found here and there;
Wiring thickness is required.

The above explanation was based on a typical example, but
The present invention is not limited to this embodiment, and various modifications and applications are possible. For example, the insulating film
Not only can various insulating films other than the SiO ₂ film be applied, but also a combination of two or more types of insulating films can be applied.
For example, in FIG. 4, a thin film 41 having a higher dielectric constant such as silicon nitride or tantalum nitride than silicon oxide is provided on the channel cut n ⁺ layer, and a silicon oxide film 4
This is an example in which an insulating film is formed by providing 2. This makes it possible to further reduce the total thickness of the insulating film on the n ⁺ layer for channel cutting, which is necessary to ensure the same breakdown voltage, and as a result, even with thinner Al wiring, breakage can be prevented. In this case, a thin film 42 having a high dielectric constant may be provided on the silicon oxide film 41.

In FIG. 4, the same reference numerals as in FIGS. 1 and 2 indicate the same or equivalent parts.

In the above explanation, each island region 3a to 3c has n-type conductivity, and the channel cut layer has the same conductivity type and is an n ⁺ layer with high impurity concentration. A similar effect can be obtained even if is p ⁺ type.

Of course, the present invention is also applicable to complementary dielectric insulation isolation substrates.

As described above, according to the present invention, since the thickness of the second insulating film on the second layer is thicker than the thickness of the second insulating film on the third layer, electric field concentration is lowered, and Since the step portion exists on the first layer, the electric field concentration is dispersed and the electric field concentration is alleviated, so that a semiconductor integrated device with high breakdown voltage can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a partial vertical cross-sectional view showing a conventional semiconductor integrated device, FIG. 2 is a partial vertical cross-sectional view showing an embodiment of the present invention, and FIG. 3 a to e are the semiconductor integrated device shown in FIG. FIG. 4 is a partial vertical cross-sectional view showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Dielectric insulating isolation substrate, 2... Polycrystalline silicon support region, 3a-3c... Single-crystal silicon island region, 4a-4c... Insulating isolation film, 5... Insulating film, 6a, 6c... Wiring .

Claims (1)

[Scope of Claims] 1. A plurality of single crystal regions are buried in a polycrystalline semiconductor support region via a first insulating film so as to be exposed on one main surface of the support region, and at least one of the single crystal island regions One is a first conductivity type exposed on the main surface of the single crystal island region.
a first conductivity type layer formed along the first insulating film between the first layer and the first insulating film, and having an end portion exposed to the main surface of the single crystal island region; a second layer having a higher impurity concentration than the first layer; and a third layer of a second conductivity type extending from the main surface of the single crystal island region into the first layer and formed away from the second layer. , a second insulating film is formed on the main surface of the single-crystal island region and the supporting region adjacent thereto, penetrates the second insulating film and makes ohmic contact with the third layer; extending over the entire boundary between the third layer and the first layer on the insulating film, and partially extending over the second layer beyond the first layer. The second insulating film has a portion located on the second layer that is thicker than a portion located on the third layer, and the step portion thereof is thicker than that of the portion located on the third layer. A semiconductor integrated device, characterized in that it is located on the first layer. 2. The semiconductor integrated device according to claim 1, wherein the impurity concentration of the second layer increases as it approaches the first insulating film. 3. In claim 1, the second insulating film includes a first portion existing on the second layer and its vicinity, and a first portion formed on the first portion and the third layer. and a second portion having a lower dielectric constant than the second portion.