JPS6353591B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrator, and more particularly to an integrator capable of correcting the bias current and offset voltage of an integrating amplifier.

Conventionally, the integrating amplifier that makes up the integrator has a bias current and an offset voltage, and these affect the output as errors. Therefore, in order to realize a high-precision integrator, it is necessary to minimize the bias current and offset voltage. Either amplifiers were used or their compensation circuits were attached externally. However, such amplifiers and correction methods are not only expensive and complicated to adjust, but also have the problem that it is extremely difficult to correct them completely to zero.

In view of these points, the present invention has a simple configuration that allows offset voltage of any magnitude to not affect the output, and to reduce the effect of bias current on the output. This is an attempt to realize an integrator.

The present invention will be explained below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an integrator according to the present invention. In the same figure, SW ₁ is the first switch,
SW ₂ is the second switch, SW ₃ is the third switch,
SW ₄ is the fourth switch. _A1 is an integrating amplifier, the input current i _x to be measured and the bias current i _B are input to its inverting input terminal (-), and the offset voltage Vos is applied to its non-inverting input terminal (+). The bias current _iB and offset voltage Vos generated in the integrating amplifier _A1 fluctuate due to factors such as temperature changes. The output terminal of the integrating amplifier A ₁ is connected to the non-inverting input terminal (+) of the differential amplifier A ₂ , and the output terminal of the differential amplifier A ₂ is connected to the series circuit of the switch SW ₃ and the integrating capacitor Cs, and to this series circuit. It is connected to the inverting input terminal (-) of the integrating amplifier _A1 via a switch _SW1 connected in parallel.
Further, the common connection point between switch SW ₃ and capacitor Cs is connected to the common line via switch SW ₂ . Further, the output of the differential amplifier A ₂ is applied to the capacitor C ₁ via the switch SW ₄ , and the voltage V _CM of this capacitor C ₁ is applied to the inverting input terminal of the differential amplifier A _{2 via the amplifier A 3 with} a gain of 1. It is guided by (-).

Note that the switches SW ₁ to _{SW 4} are driven by a control circuit (not shown).

The operation of the integrator of the present invention in such a configuration will be explained next with reference to FIG. One cycle of this integrator consists of four steps as shown in FIG. The steps will be explained in order as follows.

(1) Step This is the so-called reset period during which the switch
Turn SW ₁ and SW ₂ ON, switch SW ₃ and SW ₄ OFF
and the offset voltage on the integrating capacitor Cs
Remember Vos.

(2) Step During the bias current _iB memorization period, switches SW ₂ and SW ₄ are turned on, and switches SW ₁ and SW ₃ are turned on.
Turn it OFF and store i _B in C ₁ . That is,
If the voltage stored in C ₁ is V _CM , then {(−Vos−1/Cs∫ ^T1 ₀ i _B dt+Vos) xA ₁₁ −V _CM }・ From A ₂₁ = V _CM , V _CM = −1/Cs∫ ^T1 ₀ i _B dtx (A ₁₁・A ₂₁ /1 + A ₂₁ ) (1) However, A ₁₁ is the amplification factor of amplifier A ₁ A ₂₁ is the amplification factor of amplifier A ₂ (3) Step SW ₁ during the reset period again , Turn on SW ₂ ,
Turn off SW ₃ and SW ₄ and turn off capacitor Cs again.
to memorize Vos.

(4) Step This is an integration period, during which the input current i _x is input for the first time and integrated, but to simplify the explanation, the case where i _x =0 will be explained. Only SW ₃ is ON, other switches SW ₁ , SW ₂ ,
Turn SW ₄ OFF. Differential amplifier A ₂ in this case
The output voltage V _{put of} is as follows.

(−ε ₁・A ₁₁ −V _CM )・A ₂₁ =V _put (2) (Vos+ε ₁ )−1/Cs∫ ^T1 ₀ i _B dt−Vos=V _put (3) However, ε ₁ is the amplifier A ₁ From equations (2) and (3), (1+1/A ₁₁・A ₂₁ )V _put = −1/Cs∫ ^T1 ₀ i _B dt− 1/A ₁₁・V _CM (4) From equation (4) Substituting equation (1), (1+1/A ₁₁・A ₂₁ )V _put =−(1/1+A ₂₁ )・1/C
s ∫ ^T1 ₀ i _B dt (5) Here, since 1/A ₁₁ · A ₂₁ 0, equation (5) becomes as follows.

V _put =-(1/1+A ₂₁ )1/Cs∫ ^T1 ₀ i _B dt≒-1/A _2
1・1/Cs∫ ^T1 ₀ i _B dt (6) As is clear from equation (6), the voltage obtained by such a sequence has no influence at all from the offset voltage Vos, and moreover, the bias current
The effect of i _B is reduced by -1/A ₂₁ times.

As explained above, according to the present invention, with a simple configuration and without requiring any adjustment,
It is possible to realize an integrator that can completely correct offset voltage and reduce the influence of bias current to an almost negligible level. Furthermore, there is no need to use expensive and high-precision integrating amplifiers and other amplifiers; instead, a high-quality integrator can be realized by simply using an inexpensive amplifier that guarantees the stability of its characteristics during one cycle. There is an effect that can be done.

Also, such an integrator can be used as a CT
It is suitable for use in a current measuring device that measures ionization current from an ionization chamber for detecting transmitted radiation in a (Computerized Tomography) device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an integrator according to the present invention, and FIG. 2 is a time chart. A ₂ ... Integrating amplifier, A ₂ ... Differential amplifier, A ₃ ...
...Amplifier, Cs... Integrating capacitor, C ₁ ... Capacitor, SW ₁ , SW ₂ , SW ₃ , SW ₄ ... Switch.

Claims (1)

[Claims] 1. The output of the integrating amplifier _A1 is used as one input signal,
a differential amplifier A ₂ which uses the output of the amplifier A ₃ with a gain of 1 as the other input signal; and one end _of which is connected to the input terminal of the amplifier A ₃ and the differential amplifier
A capacitor C ₁ connected to the output terminal of A ₂ and the other end connected to the common line, and the input terminal of the integrating amplifier A ₁ and the differential amplifier.
The first switch connected between the output ends of A ₂
SW ₁ , one end of which is connected to the input end of the integrating amplifier A ₁ ;
an integrating capacitor C _s whose other end is connected to the output terminal of _{the differential amplifier A 2 via} a third switch SW 3 _;
a second switch SW ₂ connected between the connection point of SW ₃ and _the common line; amplifier
An integrator characterized in that the offset voltage and bias current at _A1 are corrected to obtain a voltage corresponding to the input current. Note: The first switch SW ₁ and the second switch SW ₂ are turned on, while the third switch SW ₃ and the fourth switch SW ₄ are turned off, and the integrating amplifier A ₁
The offset voltage of is stored in the integrating capacitor _Cs . The second switch SW ₂ and the fourth switch SW ₄ are turned on, while the first switch SW ₁ and the third switch SW ₃ are turned off, so that the integrating amplifier A ₁
Charge the T ₁ capacitor C ₁ for a certain period of time with a bias current of . The first switch SW ₁ and the second switch SW ₂ are turned on, while the third switch SW ₃ and the fourth switch SW ₄ are turned off, so that the integrating amplifier A ₁
The offset voltage of the integrating capacitor C _s
to be memorized. Only the third switch _SW3 is turned on, and the input current i _x is integrated for a certain period of time _T1 .