JPS6353727B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillator that selects a voltage divided by resistors according to the count contents of a counter and outputs a sine wave signal.

The clock is counted by an up-down counter, the count contents are decoded, an analog gate is controlled by the decoded output, and a voltage divided by a resistor is selectively output via the analog gate, thereby outputting a sine wave signal. Oscillators are known. In this conventional oscillator, an up-down counter is used as described above to output the rising and falling parts of the waveform of the sine wave signal.
For example, when a offset occurs due to an up count, the counter is controlled to shift to a down count, and its configuration has the disadvantage of being more complex than a simple binary counter.

The present invention improves the above-mentioned drawbacks of the conventional art, and aims to make it possible to generate a sine wave using a binary counter with a simple configuration. Examples will be described in detail below.

FIG. 1 is a block diagram of an embodiment of the present invention, where 1 is a binary counter, 2 is an analog gate circuit including a decoder, 3 and 4 are variable frequency dividers, and 5 and 6 are data determining the frequency division ratio. A latch circuit that latches the
7 is an inverter, CLK is a clock, OUT is an output terminal, and R1 to R7 are resistors. variable frequency divider 3,
4 indicates the case where integrated circuit MC14526 (manufactured by Motorola, USA) is used; 1 to 6, 11 to 1
4 indicates the terminal number, and the bits of latch circuits 5 and 6
It has a function to divide the frequency according to the specifications of (1) to (6). For example, when bits (1) to (6) of latch circuits 5 and 6 are set to "000001", the total frequency of the clock CLK is divided by 32. The frequency-divided output becomes a clock counted by binary counter 1.

The binary counter 1 shows the case of 4 bits, and the most significant bit Q4 controls whether or not to invert the polarity of the voltage applied to the resistors R1 to R7. For example, when the most significant bit Q4 is "1", the resistor R7 side becomes positive and the R1 side becomes a ground potential, and when the most significant bit is "0", the resistor R1 side becomes positive and the R7 side becomes a ground potential. Also resistance R1~R
The value 7 is selected so that the levels between the positive and negative maximum values of the sine wave can be sequentially obtained in eight steps. Furthermore, the lower three bits of the binary counter 1 excluding the most significant bit are input to the analog gate circuit 2, and the eight terminals a to h of the analog gate circuit 2 are selected by these three bits and connected to the output terminal OUT. .

Figure 2 is an explanatory diagram of the operation, where a is the output waveform, b
indicates the count contents of the lower three bits of the binary counter 1, and c indicates the output of the inverter 7. For example 2
Count contents of decimal counter 1 Q4, Q3, Q2,
When Q1 is “0000”, the output of inverter 7 is “1”, and the lower three bits Q3, Q2, Q1
“000” causes terminal a of analog gate circuit 2 to
is connected to the output terminal OUT, so the lowest level will be output. Also, count contents Q
4, Q3, Q2, and Q1 become "0001", the terminal b of the analog gate circuit 2 is connected to the output terminal OUT, and the level at the connection point of the resistors R6 and R7 is output. Thereafter, terminals a to h of the analog gate circuit 2 are similarly selected according to the count contents and connected to the output terminal OUT, resulting in an output whose level increases sequentially in a sine wave shape. Then, when the count contents Q4, Q3, Q2, Q1 become "0111", terminal h is selectively connected and the highest level is output, and then when the count contents Q4, Q3, Q2, Q1 become "1000", the lower 3 bits Q3, Q2, Q
1's "000" selectively connects the terminal a of the analog gate circuit 2, but since the most significant bit Q4 is "1", the output of the inverter 7 is "0".
Therefore, the voltages applied to the resistors R1 to R7 are inverted. Therefore, the highest level is also output by selectively connecting terminal a.

Count contents of binary counter 1 Q4, Q3, Q
2. When Q1 is between “1000” and “1111”, the output level decreases sequentially in a sine wave pattern, and when the count contents Q4, Q3, Q2, and Q1 are “1111”, terminal h is selectively connected and is the lowest. Then, the count contents Q4, Q3, Q2, Q1 become "0000" and the terminal a is selectively connected, but the output of the inverter 7 becomes "1" and the resistors R1 to
The polarity of the voltage applied to R7 is reversed, and the lowest level is output. By repeating this operation, a staircase-shaped sine wave shown in FIG. 2a is output. The frequency of this sine wave output is
Assuming the frequency of CLK, when the frequency is divided by N by frequency dividers 3 and 4, since binary counter 1 has 4 bits, it corresponds to the frequency further divided by 16.
/16・N.

In the above embodiment, one cycle of a sine wave is formed in 16 steps by a 4-bit binary counter 1,
The voltage applied to the resistors R1 to R7 is inverted every 8 steps, but by increasing the number of bits in the binary counter 1 and increasing the number of resistors, a sine wave with smooth level changes can be created. The variable frequency divider 3,
By increasing the number of stages (4), the range of output frequencies can be expanded.

As explained above, the present invention includes a binary counter 1, a resistor group consisting of resistors R1 to R7, etc., the output of the most significant bit of the binary counter 1 is applied to one end of this resistor group, and the output of the most significant bit of the binary counter 1 is applied to the other end. Inverter 7 is connected so as to invert and apply the output of the most significant bit to
and an analog gate circuit 2 which selects and outputs the divided voltage by the resistor group by adding the outputs of the other bits except the most significant bit of the binary counter 1. It is advantageous to have a relatively simple configuration that simply counts clocks without requiring a configuration for switching between clock and down-counting.

Further, by adding bits other than the most significant bit of the binary counter 1 to the analog gate circuit 2, the decoding function in the analog gate circuit 2 can be simplified. Furthermore, one inverter 7
By simply adding , the most significant bit of the binary counter 1 is inverted by the inverter 7, the polarity of the voltage applied to the resistor group is inverted, and the rising and falling parts of the sine waveform can be easily generated. Therefore, an economical oscillator can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation. 1 is a binary counter, 2 is an analog gate circuit,
3 and 4 are frequency dividers, 5 and 6 are latch circuits, 7 is an inverter, R1 to R7 are resistors, and CLK is a clock.

Claims (1)

[Claims] 1. A binary counter that counts clocks, a resistor group that forms a sine wave voltage by sequentially selecting divided voltages, the output of the most significant bit of the binary counter being applied to one end of the resistor group, and the other end an inverter connected to invert and apply the output of the most significant bit to the inverter; and an analog gate that adds the outputs of the other bits other than the most significant bit of the binary counter and selectively outputs the divided voltage by the resistor group. An oscillator characterized by being equipped with a circuit.