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JPS6353791B2 - - Google Patents
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JPS6353791B2 - - Google Patents

Info

Publication number
JPS6353791B2
JPS6353791B2 JP4056781A JP4056781A JPS6353791B2 JP S6353791 B2 JPS6353791 B2 JP S6353791B2 JP 4056781 A JP4056781 A JP 4056781A JP 4056781 A JP4056781 A JP 4056781A JP S6353791 B2 JPS6353791 B2 JP S6353791B2
Authority
JP
Japan
Prior art keywords
output
pulse width
voltage
switching element
output terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4056781A
Other languages
Japanese (ja)
Other versions
JPS57155631A (en
Inventor
Masanobu Kawamura
Shuichi Umemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Kiki Co Ltd
Original Assignee
Micron Kiki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Kiki Co Ltd filed Critical Micron Kiki Co Ltd
Priority to JP4056781A priority Critical patent/JPS57155631A/en
Publication of JPS57155631A publication Critical patent/JPS57155631A/en
Publication of JPS6353791B2 publication Critical patent/JPS6353791B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/22Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33561Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having more than one ouput with independent control

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 本発明はスイツチングレギユレータのマルチ出
力シーケンス回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching regulator multi-output sequence circuit.

スイツチングレギユレータのマルチ出力には、
負荷の種類により電源投入、切断のシーケンスを
必要とし、その切断のシーケンスは停電時にも確
立する必要がある。そこで従来はスイツチングレ
ギユレータにおいて交流の入力波形を検出してマ
ルチ出力のうち所定出力をスイツチング素子か、
リレー等で即時にオフし他の出力をコンデンサ等
の保持手段で保持する方式が採られている。しか
しこの方式では交流入力波形を検出することによ
つて停電を検出するので、停電の検出速度が遅
く、交流入力波形の半波を検出するにしても
10msec(50Hzの場合)を要し、保持手段はそれ以
上の保持時間をもつ大きなものが必要となり、更
に交流入力の周波数、波形歪の影響を受ける。
The multiple outputs of the switching regulator include
Depending on the type of load, a power-on and power-off sequence is required, and this power-off sequence must be established even during a power outage. Therefore, conventionally, a switching regulator detects the AC input waveform and outputs a predetermined output from among the multiple outputs to a switching element.
A method is adopted in which the output is immediately turned off using a relay or the like, and other outputs are held by a holding means such as a capacitor. However, since this method detects a power outage by detecting the AC input waveform, the detection speed of a power outage is slow, and even if it detects a half wave of the AC input waveform,
This requires 10 msec (for 50 Hz), requires a large holding means with a longer holding time, and is further affected by the frequency and waveform distortion of the AC input.

本発明は上記のような欠点を除去し、保持手段
の機能縮小が可能で交流入力の周波数、波形歪の
影響を受けないスイツチングレギユレータのマル
チ出力シーケンス回路を提供することを目的とす
る。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-output sequence circuit for a switching regulator that eliminates the above-mentioned drawbacks, allows the function of the holding means to be reduced, and is unaffected by the frequency and waveform distortion of AC input. .

以下図面を参照しながら本発明について実施例
をあげて説明する。
The present invention will be described below by way of examples with reference to the drawings.

第1図に示すように商用電源からの100Vの交
流電圧は整流回路1で整流されてコンデンサ2に
より平滑され直流電圧となる。この直流電圧はト
ランジスタ3により断続されてトランス4の1次
巻線に印加され、トランス4の各2次巻線の出力
はそれぞれダイオード5〜8で整流されてコイル
9,10及びコンデンサ11,12により平滑さ
れ出力端子13〜16より各負荷へ供給される。
制御回路17は出力端子13,14間の出力電圧
を基準電源18の基準電圧と比較してその差電圧
を増幅する。駆動回路19は制御回路17の出力
電圧に応じたパルス幅で高い周波数例えば20KHz
のパルスを発生し、このパルスはトランス20、
抵抗21を介してトランジスタ3のベース・エミ
ツタ間に印加される。トランジスタ3のオン時間
は出力端子13,14間の出力電圧が低下すれば
長くなり、逆に出力電圧が上昇すれば短かくな
り、従つて出力端子13〜16の出力電圧が安定
化される。パルス幅検出回路22は駆動回路19
の出力パルス幅が予め設定された基準パルス幅以
上になつたことを検出することによつて停電を検
出する。このパルス幅検出回路22は周知のパル
ス消滅検出回路が用いられ、スイツチング素子2
3はパルス幅検出回路22の出力信号により停電
時にオンし出力端子15,16間を短絡してその
出力電圧をオフする。スイツチング素子23はホ
ールド機能を持つサイリスタが用いられる。この
時出力端子13,14間の出力電圧はコンデンサ
2によりまだ保持されている。第2図は停電時に
おける出力端子13,14間の出力電圧Aと出力
端子15,16間の出力電圧Bのオフシーケンス
を示す。
As shown in FIG. 1, an AC voltage of 100V from a commercial power source is rectified by a rectifier circuit 1 and smoothed by a capacitor 2 to become a DC voltage. This DC voltage is interrupted by a transistor 3 and applied to the primary winding of a transformer 4, and the outputs of each secondary winding of the transformer 4 are rectified by diodes 5 to 8, respectively, to coils 9, 10 and capacitors 11, 12. The signal is smoothed by the output terminals 13 to 16 and supplied to each load.
The control circuit 17 compares the output voltage between the output terminals 13 and 14 with the reference voltage of the reference power supply 18, and amplifies the difference voltage. The drive circuit 19 has a pulse width corresponding to the output voltage of the control circuit 17 and a high frequency, for example, 20KHz.
This pulse generates a pulse of transformer 20,
It is applied between the base and emitter of the transistor 3 via the resistor 21. The on-time of the transistor 3 increases as the output voltage between the output terminals 13 and 14 decreases, and conversely decreases as the output voltage increases, so that the output voltages of the output terminals 13 to 16 are stabilized. The pulse width detection circuit 22 is the drive circuit 19
A power outage is detected by detecting that the output pulse width of the output pulse width exceeds a preset reference pulse width. This pulse width detection circuit 22 uses a well-known pulse extinction detection circuit, and the switching element 2
3 is turned on at the time of a power outage by the output signal of the pulse width detection circuit 22, short-circuiting between the output terminals 15 and 16, and turning off the output voltage. As the switching element 23, a thyristor having a hold function is used. At this time, the output voltage between the output terminals 13 and 14 is still held by the capacitor 2. FIG. 2 shows the off sequence of the output voltage A between the output terminals 13 and 14 and the output voltage B between the output terminals 15 and 16 during a power outage.

この実施例では駆動回路19からの20KHzのパ
ルスよりパルス幅検出回路22で停電を検出する
から停電検出速度は前記従来方式で50Hzの交流入
力の半波を検出する場合に比べて400倍にもなつ
て保持手段2を小さくでき、又交流入力の周波
数、波形歪の影響を受けない。又コンデンサ2の
両端電圧の降下の大小によらず出力A,Bのシー
ケンスが確立する。
In this embodiment, the pulse width detection circuit 22 detects a power outage based on the 20 KHz pulse from the drive circuit 19, so the power outage detection speed is 400 times faster than in the case of detecting a half wave of a 50 Hz AC input using the conventional method. Therefore, the holding means 2 can be made smaller, and it is not affected by the frequency and waveform distortion of AC input. Moreover, the sequence of outputs A and B is established regardless of the magnitude of the voltage drop across the capacitor 2.

なお本発明は上記実施例に限定されるものでは
なく、プツシユプル方式やハーフブリツジ方式等
のスイツチングレギユレータにも同様に適用する
ことができる。
It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be similarly applied to switching regulators such as push-pull type and half-bridge type.

以上のように本発明によれば交流入力を直流電
圧に変換してスイツチング素子で断続してトラン
スに印加しこのトランスのマルチ出力を直流電圧
に変換して複数の出力端子より出力しこのマルチ
出力電圧のうち1つに応じたパルス幅を有する高
周波数のパルスを前記スイツチング素子に加える
スイツチングレギユレータにおいて前記パルス幅
が予め設定された値以上になつたことを検出して
前記マルチ出力のうちの所定のものをスイツチン
グ素子でオフするので、停電の検出速度が早くて
保持手段の縮小が可能となり、交流入力の周波
数、波形歪の影響を受けなくなる。
As described above, according to the present invention, an AC input is converted into a DC voltage, which is intermittently applied to a transformer using a switching element, and the multiple outputs of this transformer are converted into DC voltages and outputted from multiple output terminals. A switching regulator applies a high-frequency pulse having a pulse width corresponding to one of the voltages to the switching element, detects that the pulse width exceeds a preset value, and outputs the multi-output. Since a predetermined one of them is turned off by a switching element, the detection speed of a power outage is fast, the holding means can be reduced in size, and it is not affected by the frequency and waveform distortion of the AC input.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2
図は、同実施例のタイミングチヤートである。 22…パルス幅検出回路、23…サイリスタ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a timing chart of the same embodiment. 22... Pulse width detection circuit, 23... Thyristor.

Claims (1)

【特許請求の範囲】[Claims] 1 交流入力を直流電圧に変換してスイツチング
素子で断続してトランスに印加しこのトランスの
マルチ出力を直流電圧に変換して複数の出力端子
より出力しこのマルチ出力電圧のうち1つに応じ
たパルス幅のパルスを前記スイツチング素子に加
えるスイツチングレギユレータにおいて、前記パ
ルス幅が予め設定された値以上になつたことを検
出するパルス幅検出回路と、このパルス幅検出回
路の出力信号により前記複数の出力端子のうちの
所定のものを短絡するスイツチング素子とを備え
たスイツチングレギユレータのマルチ出力シーケ
ンス回路。
1. Convert AC input to DC voltage and apply it to a transformer intermittently using a switching element, convert the multiple outputs of this transformer to DC voltage, output from multiple output terminals, and respond to one of these multiple output voltages. A switching regulator that applies a pulse with a pulse width to the switching element includes a pulse width detection circuit that detects when the pulse width exceeds a preset value; A switching regulator multi-output sequence circuit comprising a switching element that shorts a predetermined one of a plurality of output terminals.
JP4056781A 1981-03-20 1981-03-20 Multioutput sequence circuit of switching regulator Granted JPS57155631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4056781A JPS57155631A (en) 1981-03-20 1981-03-20 Multioutput sequence circuit of switching regulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4056781A JPS57155631A (en) 1981-03-20 1981-03-20 Multioutput sequence circuit of switching regulator

Publications (2)

Publication Number Publication Date
JPS57155631A JPS57155631A (en) 1982-09-25
JPS6353791B2 true JPS6353791B2 (en) 1988-10-25

Family

ID=12584042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4056781A Granted JPS57155631A (en) 1981-03-20 1981-03-20 Multioutput sequence circuit of switching regulator

Country Status (1)

Country Link
JP (1) JPS57155631A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4617722B2 (en) * 2004-05-27 2011-01-26 ダイキン工業株式会社 CONVERTER CONTROL METHOD AND CONVERTER CONTROL DEVICE

Also Published As

Publication number Publication date
JPS57155631A (en) 1982-09-25

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