JPS6354212B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device such as a diode or a thyristor, and more particularly to a method of manufacturing a semiconductor device including a step of preventing abnormal diffusion of phosphorus or the like (phosphorus spike).

A conventional manufacturing process for a semiconductor device will be briefly described with reference to FIG. 1, taking a thyristor as an example.

First, an N-type silicon substrate 10 having a resistivity of 150 Ωcm and a thickness of 455 μm is prepared. As shown in Figure 1a,
One surface of this substrate is covered with an oxide film (SiO ₂ film) 13, and an N-type impurity phosphorus is diffused at a low temperature of 1000° C. or less to form an extremely thin N ⁺ layer 11 of 1 μm or less.

Subsequently, as shown in Figure 1b, high temperature (1250
By stretching and diffusing for a long time at
The thickness of the N ⁺ layer 11 is increased to approximately 70 μm. Then, as shown in Figure 1c, P-type impurity gallium was added.
Diffused at 1100-1200℃, thin (8 μm) P ⁺ layer 1
5 and 16 are formed on both sides of the substrate 10.

Furthermore, as shown in FIG. 1d, the N ⁺ layer 11 side
After removing the P ⁺ layer 16 by chemical etching, the P ⁺ layer 15 is stretched and diffused to about 75 μm at a high temperature of about 1250° C., as shown in FIG. 1e. Through the above steps, an N ⁺ NP ⁺ junction structure is obtained.

Subsequently, as shown in Fig. 1 f, after partially removing the SiO ₂ film 13 on the P ⁺ layer 15 side, as shown in Fig. 1 g
As shown in Figure 2, by doping N-type impurity phosphorus at 1100 to 1200℃, a relatively thin
10 μm) to form an N ⁺ layer 18.

Furthermore, as shown in Figure 1h, at approximately 1250℃,
The N ⁺ layer 18 is stretched and diffused to approximately 30 μm. Subsequently, as shown in FIG. 1i, gallium impurities are diffused at about 1250° C. to form a P ⁺ layer 19. Through the above steps, a thyristor with a P ⁺ N ⁺ NP ⁺ N ⁺ structure is obtained.

Figure 2 shows the conventional process a~ shown in Figure 1.
b and d of i are shown in more detail.

As shown in FIG. 2b, if there is a pinhole or the like in the oxide film 13, an abnormal phosphorus diffusion layer - that is, a phosphorus spike N ⁺ layer 120 is locally formed, and then as shown in FIG. Then, a P ⁺ layer 15 is formed by diffusing gallium.

However, as shown, when the phosphorus spike N ⁺ layer 120 is highly concentrated and deeply diffused, the junction layer becomes locally N ⁺ NN ⁺ . If a rated voltage is applied to the N-type silicon substrate 10 in such a state, a short circuit will occur locally, resulting in the disadvantage that the rated withstand voltage cannot be obtained.

In addition, the phosphorus spike N ⁺ layer 120 is P ⁺ layer 15
When a rated voltage is applied to the substrate 10, a depletion layer extends in the P + layer 15 even if it is shallow compared to the P ⁺ layer 15 . For this reason, the distance between the depletion layer and the abnormal phosphorus diffusion region becomes extremely narrow, or the two come into contact with each other.
There is a drawback that breakover occurs at an applied voltage lower than the rated voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the drawbacks of the above-mentioned conventional techniques and eliminate the adverse effects caused by abnormal diffusion of N-type impurities such as phosphorus.

A feature of the present invention is that when an N-type impurity such as phosphorus is diffused from one surface of the N-type semiconductor substrate to form an N ⁺ layer, an abnormal diffusion region of phosphorus that occurs in the N-type semiconductor substrate is chemically removed. The final bond is formed by removing it by etching, mechanical lapping, etc., and then by diffusing gallium impurities to form a P ⁺ layer.
The point is that semiconductor devices such as diodes or thyristors are manufactured using N ⁺ NP ⁺ or P ⁺ N ⁺ NP ⁺ N ⁺ structures.

The invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

3A to 3L illustrate the manufacturing process of a thyristor according to an embodiment of the present invention.

First, an N-type silicon substrate 20 having a resistivity of 150 Ωcm and a thickness of 500 μm is prepared. As shown in Figure 3a,
One side of it is covered with an oxide film (SiO ₂ film) 23,
Diffusion of N-type impurity phosphorus at a low temperature of 1000℃ or less,
An extremely thin N ⁺ layer 21 of 1 μm or less is formed.

Subsequently, as shown in Figure 3b, a relatively low temperature (approximately
Stretching and diffusion is performed at 1100° C.) to extend the diffusion depth of the N ⁺ layer 21 to 8 μm. Here, 1200～
The purpose of not using a high temperature of about 1250°C is to prevent the depth of diffusion from becoming too deep if abnormal diffusion of phosphorus occurs.

Next, as shown in FIG. 3c, the oxide film (SiO ₂ film) 23 is removed, and the surface opposite to the side where the N ⁺ layer 21 is formed is made approximately 1.5 to 2 times the thickness of the N ⁺ layer 21. (about 12
chemical etching and mechanical polishing to a depth of ~15 μm).

The reason for this is that an abnormal diffusion of phosphorus, or so-called phosphorus spike, was detected on the opposite surface of the N ⁺ layer 21 at a depth of 8 μm, and its maximum depth was approximately 12 μm (N ⁺ layer 21). 21 depth of 8μm approximately 1.5
This is because it has been confirmed that

Subsequently, as shown in Figure 3d, high temperature (1250
N ⁺ by stretching and diffusing for a long time at
The thickness of layer 21 is approximately 70 μm. The surface concentration of the N ⁺ layer 21 at this time is two to three orders of magnitude lower than the concentration in the cases shown in FIGS. 3a to 3c.

In the step d, due to out-diffusion from the N ⁺ layer 21 or due to adhesion of phosphorus floating in the air, local abnormal diffusion of phosphorus occurs again on the other surface (upper side in the figure). may occur.

For this reason, as shown in FIG. 3e, after removing the upper oxide film (SiO ₂ film) 25, the local abnormal diffusion of phosphorus on the other surface is removed. In this case, the thickness of the removal layer may be about 30 μm.

Next, as shown in Figure 3 f, gallium was added.
Diffusion at 1100-1200℃, thin 8μm P ⁺ layer 26,
27 is formed on both sides.

Furthermore, as shown in FIG. 3g, after removing the P ⁺ layer 27 on the N ⁺ layer 21 side by chemical etching, the third
As shown in Figure h, the P ⁺ layer 26 is heated to about 1250°C.
Stretch and diffuse to 75 μm. Through the above steps, an N ⁺ NP ⁺ diode junction structure is obtained.

Subsequently, as shown in FIG. 3i, the P ⁺ layer side 26
After locally removing the SiO ₂ film 28 on one side (upper side), as shown in FIG.
By selectively diffusing phosphorus impurities at ℃, relatively thin, 8
Form a ~10 μm N ⁺ layer 30.

Subsequently, as shown in FIG. 3k, the N ⁺ layer 30 is stretched to about 30 μm at about 1250° C. and diffused.
Subsequently, as shown in FIG. 3I, gallium impurities are diffused onto the other surface (lower surface) at about 1250° C. to form a P ⁺ layer 31. Through the above steps, a thyristor element having a P ⁺ N ⁺ NP ⁺ N ⁺ structure is obtained.

The number of spikes in the sample produced in this way,
The results of comparing the maximum spike depth and breakdown voltage distribution with thyristor elements manufactured using conventional manufacturing processes are shown in the fourth section.
, 5 and 6.

FIG. 4 is a diagram showing the distribution of the number of spikes.
From this figure, it can be seen that the number of spikes is as high as about 4.5 spikes/cm ² at the maximum in the conventional process, whereas it is reduced to almost zero in the process of the present invention.

Moreover, FIG. 5 is a diagram showing the distribution of maximum spike depth. From this figure, it can be seen that the maximum spike depth reaches a maximum of 75 to 80 μm in the conventional process, whereas it is almost zero in the process of the present invention.

FIG. 6 is a diagram showing the breakdown voltage distribution. This figure shows that in the breakdown voltage distribution, there were as many as 30 samples with zero breakdown voltage when using the conventional process, whereas all samples using the process of the present invention showed the breakdown voltage as per the specifications.

From the above results, the effect of improving the withstand voltage according to the present invention was confirmed.

Note that although phosphorus has been described above as the N-type impurity, similar effects can be expected even when N-type impurities other than phosphorus, such as arsenic or antimony, are used.

In addition, in FIG. 3, after stretching and diffusing the N ⁺ layer 21 at a relatively low temperature as shown in FIG. 3b, the upper surface of the N layer 22 is removed, and then again at a high temperature as shown in Perform enlargement and diffusion with
Although the step of removing the upper surface of the layer 22 was adopted, the first step of removing the upper surface of the N layer may be omitted. With this, almost the same effect can be obtained.

In addition, in the above description, the present invention has been described as having a low reverse blocking ability.
We have described an example in which it is applied to a thyristor with a P ⁺ N ⁺ NP ⁺ N ⁺ structure, but as shown in Figure 7, it can also be applied to a reverse conduction thyristor with a P ⁺ N ⁺ NP ⁺ N ⁺ structure in which diodes are combined in antiparallel. A similar effect can be achieved by applying

In FIG. 7, the same symbols as in FIG. 3 represent the same or equivalent parts, and 32 is P ⁺
The N ^{+ layer is deeper than the layer 31 and is provided to reach the N + layer} 21 .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional thyristor manufacturing process, FIG. 2 is a detailed view of a part of the manufacturing process in FIG. 1, FIG. Figure 4 is a diagram showing a comparison of the number of spikes between the conventional method and the manufacturing method of the present invention, and Figure 5 is a comparison of the maximum spike depth between the conventional method and the manufacturing method of the present invention. FIG. 6 is a diagram showing a comparison of breakdown voltage distribution between the conventional method and the manufacturing method of the present invention, and FIG. 7 is a cross section showing the structure of another thyristor manufactured by the present invention. It is a diagram. 20...N-type silicon substrate, 21...N ⁺ layer, 22
...N layer, 26...P ⁺ layer, 30...N ⁺ layer, 31...P ⁺
layer, 32...N ⁺ layer.

Claims (1)

[Claims] 1. Covering one side of an N-type semiconductor substrate with an oxide film,
forming an N ⁺ region by diffusing N-type impurity phosphorus on the other surface; stretching and diffusing the N ⁺ region; and abnormally diffusing the N-type impurity on one surface of the N-type semiconductor substrate. and a step of diffusing P type impurities into one surface of the N type semiconductor substrate to form a P ⁺ region. Production method. 2 Cover one side of the N-type semiconductor substrate with an oxide film,
forming an N ⁺ region by diffusing N-type impurity phosphorus on the other surface; stretching and diffusing the N ⁺ region; and abnormally diffusing the N-type impurity on one surface of the N-type semiconductor substrate. forming a P ⁺ region by diffusing P-type impurities into one surface of ^the N-type semiconductor substrate; a step of diffusing an N-type impurity phosphorus to form a second N ⁺ region exposed on one surface; and a step of diffusing a P-type impurity into the N ⁺ region formed on the other surface to form a second N+ region exposed on the other surface. A method of manufacturing a semiconductor device, comprising the step of: forming a second P ⁺ region exposed to . 3 Cover one side of the N-type semiconductor substrate with an oxide film,
forming an N ⁺ region by diffusing N-type impurity phosphorus on the other surface; stretching and diffusing the N ⁺ region; and abnormally diffusing the N-type impurity on one surface of the N-type semiconductor substrate. a step of further stretching and diffusing the N ^{+ region; and a step of removing the N+} region generated in the second stretching and diffusing step from one side of the N-type semiconductor substrate. The present invention is characterized by comprising the steps of: removing only a sufficient thickness to remove abnormal diffusion of type impurities; and forming a P ⁺ region by diffusing P type impurities on one surface of the N type semiconductor substrate. A method for manufacturing a semiconductor device. 4 The thickness of the semiconductor substrate to be removed first is approximately the thickness of the N ⁺ region formed on the other side at that time.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the manufacturing method is 1.5 to 2.0 times. 5 Cover one side of the N-type semiconductor substrate with an oxide film,
forming an N ⁺ region by diffusing N-type impurity phosphorus on the other surface; stretching and diffusing the N ⁺ region; and abnormally diffusing the N-type impurity on one surface of the N-type semiconductor substrate. a step of further stretching and diffusing the N ^{+ region; and a step of removing the N+} region generated in the second stretching and diffusing step from one side of the N-type semiconductor substrate. removing a sufficient thickness to remove abnormal diffusion of type impurities; forming a P+ region by diffusing P-type impurities on one surface of the N-type semiconductor substrate; and forming a P ⁺ region in the P ⁺ region. a step of diffusing phosphorus as an N-type impurity into a part of the surface to form a second N ⁺ region exposed on one surface; and diffusing a P-type impurity into the N ⁺ region formed on the other surface. and forming a second P ⁺ region exposed on the other surface. 6 The thickness of the semiconductor substrate to be removed first is approximately the thickness of the N ⁺ region formed on the other side at that time.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the manufacturing method is 1.5 to 2.0 times.