Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS6354223B2 - - Google Patents
[go: Go Back, main page]

JPS6354223B2 - - Google Patents

Info

Publication number
JPS6354223B2
JPS6354223B2 JP58074021A JP7402183A JPS6354223B2 JP S6354223 B2 JPS6354223 B2 JP S6354223B2 JP 58074021 A JP58074021 A JP 58074021A JP 7402183 A JP7402183 A JP 7402183A JP S6354223 B2 JPS6354223 B2 JP S6354223B2
Authority
JP
Japan
Prior art keywords
semiconductor element
recess
bonding material
heat sink
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58074021A
Other languages
Japanese (ja)
Other versions
JPS59200447A (en
Inventor
Sadayuki Sone
Haruo Yamanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58074021A priority Critical patent/JPS59200447A/en
Publication of JPS59200447A publication Critical patent/JPS59200447A/en
Publication of JPS6354223B2 publication Critical patent/JPS6354223B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07336Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置に関し、特に半導体素子
を放熱板に取着する一例の電力用半導体装置の組
立構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to an assembly structure of a power semiconductor device in which a semiconductor element is attached to a heat sink.

〔発明の技術的背景〕 従来のハイブリツドICモジユールに第1図に
示されるものがある。その外囲器1はわく型のケ
ース本体2と、このケース本体の一方の開端を閉
塞するふた状のカバー3と、ケース本体の他方の
開端に密接し後述のユニツトを取着けるベース4
とからなつており、また外囲器の外側には端子
5,5…が設けられている。次に、ベースの外囲
器内主面にはパワーサブユニツト6、コントロー
ルユニツト7などが配設され、さらに外囲器内に
はゲル状のレジン(図示省略)が充填されてい
る。
[Technical Background of the Invention] A conventional hybrid IC module is shown in FIG. The envelope 1 includes a frame-shaped case body 2, a lid-like cover 3 that closes one open end of the case body, and a base 4 that is in close contact with the other open end of the case body and on which a unit to be described later can be attached.
Terminals 5, 5, . . . are provided on the outside of the envelope. Next, a power subunit 6, a control unit 7, etc. are disposed on the main surface inside the envelope of the base, and the envelope is further filled with a gel-like resin (not shown).

この発明は叙上のパワーサブユニツト6部の改
良にあるので、該部の従来構造を第2図によつて
説明する。絶縁板8には通常セラミツク基板が用
いられ、これに放熱板9が積層して設けられ、こ
の放熱板にはニツケルめつきの施された銅板が用
いられている。そして、放熱板にパワートランジ
スタチツプである半導体素子10が取着され、そ
の半導体素子の一部の電極はボンデイングワイヤ
11,11…によつて導出される。また、放熱板
9には半導体素子のコレクタリード引出し用パツ
ド12が設けられている。なお、放熱板に半導体
素子の接着、および放熱板と絶縁板との接着はい
ずれもはんだ接合により達成され、第2図bには
はんだ層13,13が示される。
Since this invention consists in improving the above-mentioned power subunit 6, the conventional structure of this section will be explained with reference to FIG. A ceramic substrate is usually used as the insulating plate 8, and a heat sink 9 is laminated thereon, and the heat sink is a copper plate plated with nickel. A semiconductor element 10, which is a power transistor chip, is attached to the heat sink, and some electrodes of the semiconductor element are led out by bonding wires 11, 11, . . . . Further, the heat sink 9 is provided with a pad 12 for drawing out the collector lead of the semiconductor element. The bonding of the semiconductor element to the heat sink and the bond between the heat sink and the insulating plate are both accomplished by soldering, and FIG. 2b shows the solder layers 13, 13.

上記はんだ接合によりパワートランジスタのよ
うに発熱量の大きい半導体素子を取着する場合、
放熱を充分配慮する必要がある。これは、はんだ
層の熱抵抗が比較的大きいためで、はんだ層の厚
さはなるべく薄くすることが望ましい。しかし、
はんだ層厚が小の場合、半導体素子と放熱板との
熱膨張係数の違いにより発生した応力が半導体素
子に印加され、割れ、素子特性の劣化などが発生
する。また、はんだ層にも応力が印加されるので
はんだの劣化が生じやすくなることが知られてい
る。
When attaching a semiconductor element that generates a large amount of heat, such as a power transistor, using the above solder joint,
It is necessary to give sufficient consideration to heat dissipation. This is because the solder layer has a relatively high thermal resistance, and it is desirable to make the thickness of the solder layer as thin as possible. but,
When the solder layer thickness is small, stress generated due to the difference in thermal expansion coefficient between the semiconductor element and the heat sink is applied to the semiconductor element, causing cracking, deterioration of element characteristics, etc. Furthermore, it is known that stress is applied to the solder layer, which tends to cause deterioration of the solder.

叙上からはんだ層の層厚をコントロールするこ
とは寿命や特性を延ばす上で非常に重要な要素に
なつている。
As mentioned above, controlling the thickness of the solder layer has become a very important factor in extending the life and characteristics.

〔背景技術の問題点〕[Problems with background technology]

半導体素子と放熱板との間のはんだ層厚は経験
的に40〜50μm程度を目標にしているが、このた
めに、はんだの供給量と、はんだ溶融時に半導体
素子に加える重量(加圧)ではんだ層厚をコント
ロールしていたが、はんだ層厚にばらつきを生じ
たり、半導体素子が放熱板上面と非水平になつた
り、位置ずれを生じたりなど種々の問題点があつ
た。
Empirically, the solder layer thickness between the semiconductor element and the heat sink is targeted to be about 40 to 50 μm, but to achieve this, the amount of solder supplied and the weight (pressure) applied to the semiconductor element when melting the solder have to be adjusted. Although the solder layer thickness was controlled, there were various problems such as variations in the solder layer thickness, the semiconductor element becoming non-horizontal with the top surface of the heat sink, and misalignment.

上記の原因として、はんだの供給量が一定して
いても、構造上半導体素子の直下にはんだが溜ま
つていないので、直下から側方へ流出するはんだ
量がコントロールできないことも一因であつた。
One of the reasons for the above is that even if the amount of solder supplied is constant, the solder does not accumulate directly under the semiconductor element due to its structure, so the amount of solder flowing out from directly below to the side cannot be controlled. .

そこで、半導体素子をはんだ接合させるとき、
熱膨張係数が半導体素子に近いモリブデン板やベ
リリウム板の放熱板を用いる手段は有効である
が、これらはいずれも高価である欠点があるた
め、前記一般の放熱板を用いた改良構造が強く要
望されていた。
Therefore, when soldering semiconductor elements,
Although it is effective to use heat sinks made of molybdenum plates or beryllium plates, which have thermal expansion coefficients close to those of semiconductor elements, they both have the disadvantage of being expensive, so there is a strong demand for an improved structure using the above-mentioned general heat sinks. It had been.

〔発明の目的〕[Purpose of the invention]

この発明は上記従来の問題点を改良し要望に応
えるためになされたもので、半導体素子と放熱板
とを接合するはんだの層厚を一定にする改良構造
を提供する。
The present invention has been made to improve the above-mentioned conventional problems and meet the demands, and provides an improved structure in which the thickness of the solder layer that joins the semiconductor element and the heat sink is constant.

〔発明の概要〕[Summary of the invention]

この発明にかかる半導体装置は、半導体素子取
着面にこの半導体素子の主面よりも小なる面積の
凹部を設け、凹部に接合材を充填して半導体素子
を接着させるとともにこの凹部に連通し半導体素
子の直下から側方に延出して形成された接合材貯
留用凹部を具備したことを特徴とするものであ
る。次に放熱板に半導体素子を定位に取着するた
めの凹部を設け、この凹部底に接合材を充填する
別の凹部を設け、この凹部をさらに半導体素子の
直下から側方に延出した接合材貯留用凹部を具備
したことを特徴とするものである。
In the semiconductor device according to the present invention, a recess having an area smaller than the main surface of the semiconductor element is provided on the semiconductor element mounting surface, and the recess is filled with a bonding material to bond the semiconductor element, and the semiconductor element is connected to the recess and the semiconductor element is connected to the recess. The device is characterized in that it includes a bonding material storage recess that is formed to extend laterally from directly below the element. Next, a recess is provided in the heat sink for fixing the semiconductor element in the correct position, another recess is provided at the bottom of this recess to be filled with bonding material, and this recess is further extended laterally from directly below the semiconductor element for bonding. It is characterized by having a recess for storing material.

〔発明の実施例〕[Embodiments of the invention]

以下にこの発明を1実施例につき図面を参照し
て詳細に説明する。
Hereinafter, one embodiment of the present invention will be explained in detail with reference to the drawings.

1実施例のパワーサブユニツトの半導体素子と
放熱板との接合構造を示す第3図において、21
は放熱板で一例のニツケルめつきが施された銅
板、22は放熱板における半導体素子取着部に半
導体素子の主面よりも小に形成された凹部で、こ
の凹部にはんだが充填され、かつ凹部上にふたを
するように半導体素子10が取着されている。こ
の半導体素子は図示のように四つ角(かど)部1
0aが放熱板21の上面に密接して安定に固定さ
れている。上述の半導体素子を放熱板に接着させ
る接合材のはんだ23で、このはんだは半導体素
子の直下部分の凹部22a内を充たすとともに、
凹部が半導体素子の直下から側方へ延出した接合
材貯留用凹部22bを充たしている。
In FIG. 3 showing the bonding structure between the semiconductor element and the heat sink of the power subunit of the first embodiment, 21
22 is a heat sink, which is a copper plate plated with nickel, and 22 is a recess formed in the semiconductor element mounting portion of the heat sink to be smaller than the main surface of the semiconductor element; this recess is filled with solder; A semiconductor element 10 is attached to cover the recess. This semiconductor element has four corner parts 1 as shown in the figure.
0a is closely and stably fixed to the upper surface of the heat sink 21. The solder 23 is a bonding material for bonding the semiconductor element to the heat sink, and this solder fills the recess 22a directly below the semiconductor element, and
The recess fills a bonding material storage recess 22b extending laterally from directly below the semiconductor element.

上記はんだは第4図に示すように、予め、凹部
の深さよりも若干厚く、かつ、凹部に自在に装入
できる大きさの板状に切断されて供給される。そ
して所定位置に半導体素子を置くことにより、こ
の半導体素子は上記板状はんだ上に載置される。
次に半導体素子に固定用の鍾を載せ水素炉等に入
れてはんだを溶融させる。はんだが溶融すると半
導体素子は微かに下降しその四つ角部で放熱板の
上面に密接する。ついで炉から取り出し徐冷す
る。はんだは次第に凝固しはじめるとき、その体
積の縮減をみるが、半導体素子の直下より側方に
延出した接合材貯留用凹部があるため、体積縮減
による収縮力が分散され、半導体素子自体には大
きな応力が発生しない。
As shown in FIG. 4, the solder is supplied in advance by being cut into plate shapes that are slightly thicker than the depth of the recess and of a size that can be freely inserted into the recess. By placing the semiconductor element in a predetermined position, the semiconductor element is placed on the solder plate.
Next, a fixing peg is placed on the semiconductor element, and the semiconductor element is placed in a hydrogen furnace or the like to melt the solder. When the solder melts, the semiconductor element slightly descends and comes into close contact with the top surface of the heat sink at its four corners. Then, it is removed from the oven and allowed to slowly cool. As the solder gradually begins to solidify, its volume shrinks, but since there is a recess for storing the bonding material that extends laterally from just below the semiconductor element, the shrinkage force due to volume reduction is dispersed, and the semiconductor element itself does not No large stress occurs.

上記凹部は一例として50μでよく、放熱板を打
抜き成形するときこれを同時に設けることができ
るので、製造工程の工数も増加せず、また能率の
低下もない。
As an example, the recessed portion may be 50 μm in size, and can be provided at the same time when the heat sink is punched and formed, so that the number of man-hours in the manufacturing process does not increase and there is no decrease in efficiency.

なお、第5図a〜cはいずれも夫々が別の実施
例を示し、図中22は凹部、22bは接合材貯留
用凹部、23bは接合材貯留用凹部のはんだ層を
夫々を示す。
5A to 5C each show a different embodiment, and in the figures, 22 represents a recess, 22b represents a recess for storing a bonding material, and 23b represents a solder layer in the recess for storing a bonding material.

次に、本願の第2の発明の1実施例を第6図以
降によつて詳述する。図において、21は放熱
板、31は第1の凹部で半導体素子10を取着す
る定位に設けられ、この凹部の底に半導体素子の
主面より小に方形の第2の凹部32が形成されて
いる。この第2の凹部内にはんだ33を予めこの
凹部の形状でその深さより微かに厚い箔状に形成
されたはんだ片で装入し、半導体素子10を載せ
ると半導体素子はまず第1の凹部31内のはんだ
片上に載置され、ついではんだが溶融すると半導
体素子の四つ角部分が第1の凹部31の底面に接
触して定位に固定される。この場合、第2の凹部
32内のはんだ33で、半導体素子の下部のはん
だ33aはこの半導体素子の取着に寄与し、半導
体素子の側方のはんだ33b(第6図には交斜線
を施して示した)は接合材貯留用凹部32b内の
はんだ層になる。
Next, one embodiment of the second invention of the present application will be described in detail with reference to FIG. 6 and subsequent figures. In the figure, 21 is a heat dissipation plate, 31 is a first recess provided in a fixed position for mounting the semiconductor element 10, and a second rectangular recess 32 smaller than the main surface of the semiconductor element is formed at the bottom of this recess. ing. When the solder 33 is placed in advance in this second recess using a solder piece formed in the shape of a foil and slightly thicker than the depth of the recess, and the semiconductor element 10 is placed on the solder 33, the semiconductor element first moves into the first recess 31. When the solder melts, the four corners of the semiconductor element come into contact with the bottom surface of the first recess 31 and are fixed in position. In this case, with the solder 33 in the second recess 32, the solder 33a at the bottom of the semiconductor element contributes to the attachment of the semiconductor element, and the solder 33b at the side of the semiconductor element (crosshatched in FIG. 6) contributes to the attachment of the semiconductor element. ) is the solder layer in the bonding material storage recess 32b.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、半導体素子の下部に配され
る接合材層の層厚が凹部によつて一定化できるこ
とと、接合材貯留用凹部によつて接合材の剰余量
を半導体素子の直下から逃がし貯留させて効果が
ある。
According to this invention, the thickness of the bonding material layer disposed below the semiconductor element can be made constant by the recess, and the surplus amount of the bonding material can be released from directly below the semiconductor element by the bonding material storage recess. It is effective to store it.

次に第2の発明は、半導体素子を定位させるた
めの第2の凹部を設けて上記発明をさらに改良し
たものである。
Next, the second invention further improves the above invention by providing a second recess for orienting the semiconductor element.

叙上の如くして、形成される半導体装置の品質
の顕著な向上と、製造工程の自動化に寄与すると
ともに工程歩留の向上が達成された。
As described above, the quality of semiconductor devices formed has been significantly improved, the manufacturing process has been automated, and the process yield has been improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はハイブリツドICモジユールの組立を
説明するための斜視図、第2図は第1図のパワー
サブユニツト部を示す図aは斜視図、同図bは断
面図、第3図はこの発明の1実施例のパワーサブ
ユニツト部を示す図aは斜視図、同図bは断面
図、第4図は第3図の構成を説明するための斜視
図、第5図aないしcはいずれも夫々がこの発明
の別の実施例を示す上面図、第6図ないし第8図
は第2の発明にかかり、第6図は上面図、第7図
は第6図のAA′線に沿う矢視方向の断面図、第8
図は第6図に破線で円形に囲む部分の断面図であ
る。 10…半導体素子、10a…半導体素子の四つ
角部、21…放熱板、22a…半導体素子直下の
凹部、22b…接合材貯留用凹部(半導体素子側
方の凹部)、23a…半導体素子直下のはんだ層、
23b…接合材貯留用凹部のはんだ層、31…第
1の凹部、32a…半導体素子直下の第2の凹
部、32b…接合材貯留用凹部、33a…第2の
凹部内のはんだ層、33b…接合材貯留用凹部内
のはんだ層。
Figure 1 is a perspective view for explaining the assembly of a hybrid IC module, Figure 2 is a perspective view of the power subunit in Figure 1, Figure a is a perspective view, Figure b is a sectional view, and Figure 3 is a diagram of the present invention. FIG. 4 is a perspective view for explaining the configuration of FIG. 3, and FIGS. Each of FIGS. 6 to 8 is a top view showing another embodiment of the present invention, FIG. 6 is a top view, and FIG. 7 is a top view taken along the line AA' in FIG. 6. Sectional view in the viewing direction, No. 8
The figure is a cross-sectional view of the portion circled by a broken line in FIG. 6. DESCRIPTION OF SYMBOLS 10... Semiconductor element, 10a... Four corners of semiconductor element, 21... Heat sink, 22a... Recessed part just below semiconductor element, 22b... Recessed part for bonding material storage (recessed part on the side of semiconductor element), 23a... Solder layer just below semiconductor element ,
23b...Solder layer in the recess for bonding material storage, 31...First recess, 32a...Second recess directly below the semiconductor element, 32b...Recess for bonding material storage, 33a...Solder layer in the second recess, 33b... Solder layer in the recess for storing bonding material.

Claims (1)

【特許請求の範囲】 1 半導体素子の1主面を接合材によつて放熱板
に接合した半導体装置において、放熱板の半導体
素子取着部に半導体素子の主面よりも小に形成さ
れた凹部と、前記凹部に充填された接合材と、前
記接合材によつて放熱板に接着された半導体素子
と、前記凹部に連通し半導体素子の直下から側方
に延出された接合材貯留用凹部とを具備したこと
を特徴とする半導体装置。 2 半導体素子の1主面を接合材によつて放熱板
に接合した半導体装置において、放熱板の半導体
素子取着部に半導体素子を定位に取着する第1の
凹部と、前記第1の凹部底に半導体素子の主面よ
り小に形成された第2の凹部と、前記第2の凹部
に充填された接合材と、前記接合材によつて第1
の凹部に接着された半導体素子と、前記第2の凹
部に連通し半導体素子の直下から側方に延出され
た接合材貯留用凹部とを具備したことを特徴とす
る半導体装置。
[Scope of Claims] 1. In a semiconductor device in which one main surface of a semiconductor element is bonded to a heat sink using a bonding material, a recess formed in a semiconductor element mounting portion of the heat sink that is smaller than the main surface of the semiconductor element. a bonding material filled in the recess, a semiconductor element bonded to the heat sink by the bonding material, and a recess for storing the bonding material that communicates with the recess and extends laterally from directly below the semiconductor element. A semiconductor device comprising: 2. In a semiconductor device in which one principal surface of a semiconductor element is bonded to a heat sink using a bonding material, a first recess for fixing the semiconductor element in a fixed position in a semiconductor element attachment portion of the heat sink, and the first recess. a second recess formed at the bottom to be smaller than the main surface of the semiconductor element; a bonding material filled in the second recess; and a first recess formed by the bonding material.
A semiconductor device comprising: a semiconductor element bonded to the recess; and a bonding material storage recess communicating with the second recess and extending laterally from immediately below the semiconductor element.
JP58074021A 1983-04-28 1983-04-28 Semiconductor device Granted JPS59200447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58074021A JPS59200447A (en) 1983-04-28 1983-04-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58074021A JPS59200447A (en) 1983-04-28 1983-04-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59200447A JPS59200447A (en) 1984-11-13
JPS6354223B2 true JPS6354223B2 (en) 1988-10-27

Family

ID=13535042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58074021A Granted JPS59200447A (en) 1983-04-28 1983-04-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59200447A (en)

Also Published As

Publication number Publication date
JPS59200447A (en) 1984-11-13

Similar Documents

Publication Publication Date Title
JP3650001B2 (en) Semiconductor device and manufacturing method thereof
US6482674B1 (en) Semiconductor package having metal foil die mounting plate
CN100409434C (en) Semiconductor module and manufacturing method thereof
JP3316714B2 (en) Semiconductor device
US5834835A (en) Semiconductor device having an improved structure for storing a semiconductor chip
JP2001326236A (en) Method for manufacturing semiconductor device
JP2009295959A (en) Semiconductor device, and method for manufacturing thereof
JPS6324647A (en) Semiconductor package
JPH05109975A (en) Resin-sealed type semiconductor device
US20050142691A1 (en) Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device
JP2003078105A (en) Stack chip module
EP1195813A2 (en) Semiconductor device, semiconductor module and hard disk
JP4385324B2 (en) Semiconductor module and manufacturing method thereof
JPH04179263A (en) Resin-sealed semiconductor device, and manufacture thereof
JP2002270647A (en) Semiconductor chip mounting board and method of manufacturing the same
JP3634735B2 (en) Semiconductor device and semiconductor module
US12476218B2 (en) Semiconductor device manufacturing method
US6111309A (en) Semiconductor device
JP3082170B2 (en) Peltier element for wire bonding
JPS6354223B2 (en)
JP3215254B2 (en) High power semiconductor devices
JP3295987B2 (en) Method for manufacturing semiconductor device
JPS63169749A (en) Semiconductor device
JPS59136953A (en) Composite element
JPH0525182B2 (en)