JPS6355241B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked demodulation circuit used in a color signal processing circuit of a color television receiver.

When this type of circuit is formed as an IC, it is usually configured in a double-balanced type using NPN transistors, as shown in FIG. In FIG. 1, 1 is a BY demodulation circuit, and one transistor T ₁₀₄ of the lower differential pair is given a fixed bias (+V ₂ ), while the other transistor T ₁₀₅ is Since a chrominance signal is given, this chrominance signal is
The signals are generated in the collector of T ₁₀₄ in the same phase and in the collector of the transistor T ₁₀₅ in opposite phase, and are supplied to the emitters of the transistors T ₁₀₀ , T ₁₀₁ , T ₁₀₂ , and T ₁₀₃ that constitute the upper differential pair, respectively. One side coupling capacitor C ₄
The color subcarrier CW is applied from the emitter of the emitter follower transistor _T98 to the bases of transistors _T101 and _T102 . At that time, a color subcarrier is applied to the BY demodulation circuit 1 by the phase shift circuit 3 formed by the resistors R ₁₂₈ , R _A and the capacitors C _A and C _B , and the color subcarrier is applied to the RY demodulation circuit 2 described later. A 90° phase difference occurs between the color subcarrier and the color subcarrier.
Since the bases of the transistors T ₁₀₀ and T ₁₀₃ are connected to point A, they are connected to the bases of the transistors T ₁₀₁ and T ₁₀₂ .
The base potentials of T ₁₀₀ and T ₁₀₃ are in opposite phase to each other,
When transistors T ₁₀₁ and T ₁₀₂ are on, T ₁₀₀ ,
T ₁₀₃ is off, T ₁₀₁ , T ₁₀₂ is off, T ₁₀₀ ,
T ₁₀₃ turns on.

The above phase shift circuit is described in, for example, Japanese Utility Model Publication No. 55-33747, which has already been proposed by the applicant of the present application.
A detailed description will be omitted here. The RY demodulation circuit 2 basically has the same configuration as the BY demodulation circuit 1, and the color subcarrier and the base bias of the upper differential pair are applied from point A. the transistor
At T ₁₀₀ , T ₁₀₁ , T ₁₀₂ , and T ₁₀₃ , phase synchronized detection of the chrominance signal and color subcarrier is performed, and the first output of BY is connected to the point RO where the collectors of transistors T ₁₀₀ and T ₁₀₂ are commonly connected. 4 is generated with negative polarity, while the second output 5 of BY is generated with positive polarity at point C where the collectors of transistors T ₁₀₁ and T ₁₀₃ are commonly connected. In addition, _C5 is a capacitor for high frequency rejection,
R ₁₂₄ and R ₁₂₅ are load resistances.

By the way, when the amplitude of the first output 4 of the above-mentioned BY becomes large and the potential at point R becomes lower than the base potential of the transistors T ₁₀₀ and T ₁₀₂ , the transistors T ₁₀₀ and
The base and collector of T ₁₀₂ become forward biased, and the transistors T ₁₀₀ and T ₁₀₂ become saturated.
In this case, the input impedance of the transistors T ₁₀₀ and T ₁₀₂ decreases, and the phase of the color subcarrier CW applied via the coupling capacitor C ₄ , the transistor T ₉₈ and the phase shift circuit 3 changes, so that points B and C are reached. The demodulated outputs 4 and 5 obtained will be inaccurate.

Incidentally, in recent years, the power supply voltage (+V _CC ) of an IC has tended to be lowered, for example from 18V to 12V, for the purpose of reducing power consumption. On the other hand, by lowering the power supply voltage in an IC, the breakdown voltage of the transistor can be lowered, but lowering the breakdown voltage generally increases the current amplification rate β. The saturation of the transistors T ₁₀₀ and T ₁₀₂ described above is more likely to occur as the current amplification rate β increases if the power supply voltage is the same.

Therefore, countermeasures against the above-mentioned shortcomings are urgently needed.

The present invention has been made in view of these drawbacks, and it is an object of the present invention to propose a phase-locked demodulation circuit that suitably eliminates the saturation.

The following will explain the embodiments shown in the drawings.

In FIG. 2, in which the present invention is implemented, the same parts as in FIG. ₁ are given the same symbols for convenience of explanation. ₁₀₀ , a transistor constituting a means for clipping to a potential higher than the base potential of the transistor _T102 , its collector is connected to the power supply line 6, its emitter is connected to the point R, and its base is connected to the transistor _T100 ,
They are connected to two points of the bias (+V ₃ ) supply line 7 of T ₁₀₁ , T ₁₀₂ , and T ₁₀₃ , respectively.

Now, when the signal amplitude increases and the potential at point R drops to near the base potential of transistors T ₁₀₀ and T ₁₀₂ (slightly higher than the base potential), the transistors
Since T ₁₁₅ turns on and clips the potential at the point L near the base potential, the base and collector of transistors T ₁₀₀ and T ₁₀₂ are not forward biased (therefore, the color subcarrier is transferred from the base side to the collector side). ), and the input impedances of transistors T ₁₀₀ and T ₁₀₂ do not change. Therefore, demodulated outputs 4 and 5 are accurate.

In Figure 2, the potential at point R is clipped higher than the base potential of transistor T ₁₀₀ by the voltage drop caused by resistors R ₁₂₀ and R ₁₂₉ , while the potential at point R is clipped higher than the base potential of transistor T ₁₀₂ by the voltage drop caused by resistor R ₁₂₀ . However, without being limited to this embodiment, the clip potential at the point R is the transistor T ₁₀₀ ,
T ₁₀₂ may be chosen freely as long as it is set so that the base collector is not forward biased at any signal amplitude.

Figure 3 shows the RY demodulation circuit 2 which is the circuit of Figure 2.
and peripheral circuits are specifically shown, including transistors T ₁₀₇ , T ₁₀₈ , T ₁₀₉ , T ₁₁₀ , T ₁₁₁ ,
Similarly, for the RY demodulation circuit 2, which is configured in a double-balanced manner with T ₁₁₂ , T ₁₁₄ , resistor R ₁₂₆ , capacitor C ₆ , etc., the potential at the point where the collectors of transistors T ₁₀₇ and T ₁₀₉ are connected is _T107 , _T109
A transistor T ₁₁₆ is provided for clipping to approximately the base potential of the transistor T 116 and is connected in the same manner as the transistor T ₁₁₅ described above. This prevents saturation of the demodulation transistor in the RY demodulation circuit 2 as well as the BY demodulation circuit 1, thereby avoiding the above-mentioned disadvantages. still,
In Figure 3, _T113 is a constant current source transistor for the GY demodulation circuit, _R115 is a matrix resistor, _C6 is a high frequency rejection capacitor for RY,
_C7 is a high frequency rejection capacitor for G-Y, _T117 ,
T ₁₁₈ and T ₁₁₉ are for G-Y, RY, and B-, respectively.
Emitter follower transistor for Y, T ₁₃₉ ,
R ₁₄₀ , R ₁₄₁ , and R ₁₄₂ are the emitter resistances. From point F, the B-Y demodulated output is given to the color killer circuit and the ACC detection circuit, while from point G, the R-Y demodulated output is supplied to the color killer circuit, and from point H, the R-Y demodulated output is supplied to the ACC detection circuit. A demodulated output is given. However, the demodulated outputs taken from these points F, G, and C are respectively processed by color killer circuits and
Only the output of the color burst period is used in the ACC detection circuit. 8, 9, and 10 are BY, RY, and GY output terminals, respectively. (+
V ₁ ) are constant current source transistors T ₁₀₆ , T ₁₁₃ , T ₁₁₄
This is the bias power supply. Chroma signal is capacitor
It is applied to the bases of transistors T ₁₀₅ and T ₁₁₁ through C ₃ and emitter follower transistor T ₉₅ . The bias of transistors T ₁₀₄ and T ₁₁₂ is the resistance
_R111 , _R112 , _R115 , _R116 , _R118 , transistor
It is given by a constant voltage circuit formed from _T93 , _T96, etc.

As explained above, according to the present invention, in a phase-locked demodulation circuit constructed in a double-balanced manner using NPN transistors, means is provided for clipping the collector potential of the upper stage transistor that produces an output to the collector at a potential higher than its base potential. Since the collector potential is prevented from becoming lower than the base potential by providing the filter, the demodulation transistor is prevented from being saturated and color distortion occurs no matter how large the signal amplitude is, which is effective. Furthermore, by using the circuit of the present invention in a phase-locked demodulation circuit for video detection and appropriately setting the base bias of the transistor _T115 , white peak noise can be prevented.

Furthermore, by forming the emitter follower transistor T ₉₈ and the transistor T ₁₁₅ with the same configuration in the same IC, the temperature characteristics can be made completely the same, so even if temperature fluctuations occur, the high-grade transistor The collector potential can be held more accurately than its base potential.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional phase-locked demodulation circuit. FIG. 2 is a circuit diagram of a phase-locked demodulation circuit embodying the present invention, and FIG. 3 is a circuit diagram showing further details thereof. T ₁₀₀ - T ₁₀₃ ... Upper stage differential pair transistors for B-Y demodulation, T ₁₀₇ - _{T 110} ... Upper stage differential pair transistors for R-Y demodulation, T ₁₁₅ , T ₁₁₆ ... Clipping transistors.

Claims (1)

[Claims] 1. In a phase-locked demodulation circuit configured in a double-balanced type using NPN transistors, one end is connected to a resistor, a base is connected to the other end of this resistor, and an emitter is connected to the double-balanced type. The emitter follower transistor connected to the base of the upper transistor forms a base bias supply path for the upper transistor, and the emitter is connected to the collector of the upper transistor, the base is connected to one end of the resistor, and the collector is connected to the power source. A phase-locked demodulation circuit comprising a transistor connected to a line and clipping the collector potential of the upper transistor at a potential equal to the base potential plus the voltage drop across the resistor. 2. The phase-locked demodulation circuit according to claim 1, wherein the upper stage transistor is a transistor that produces an output in a negative direction.