JPS6355719B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a frame buffer device that temporarily stores data in units of frames and outputs data while maintaining synchronization. In general, digital data such as audio and images is composed of continuous frame-by-frame data. However, if the data transfer speed in frame units is different from the speed at which actual waveforms are generated from that data, the buffer device temporarily stores the transferred data in frame units to achieve synchronization. It is necessary to output data and generate waveforms. However, even in this case, if the frame-by-frame data transfer cannot keep up with waveform generation, waveform dropouts will occur. This invention was made in view of the above-mentioned circumstances, and even if the transfer of data in units of frames cannot keep up with the speed of the output device that receives and outputs the data, it can compensate for this and transfer data in units of frames without interruption. An object of the present invention is to provide a frame buffer device that can output from an output device. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows its configuration, and shows a case where this frame buffer device is applied to, for example, a speech synthesis device. In the figure, 11 is a multiplexer, and this multiplexer 11 is supplied with, for example, 8-bit parallel waveform data from an audio waveform data transfer device (not shown). As shown in Figure 2, this waveform data consists of one frame of data consisting of multiple pieces of 8-bit data arranged in series, and at the end of the frame, for example, all 8 bits are "1". An end code expressed as "FF" in hexadecimal is written. Third
The figure shows a model of the content of the data in one frame. In this case, to generate analog waveform data forming one voice, a plurality of pieces of digital information are stored. The frame data configured in this manner is sequentially supplied to the multiplexer 11 in 8-bit parallel fashion. Furthermore, this multiplexer 11 is supplied with a read/write control instruction signal R/W in response to the above-mentioned data transfer. The above frame data is a signal supplied to the multiplexer 11 from the status register 12, which will be described later.
Depending on the logic level state of MPX1, it is taken out so as to be distributed and switched to the DAI bus or the DBI bus, which becomes the first and second output buses. Specifically, when the signal MPX1 is at the "1" level, frame data is taken out to the DAI bus and stored in the RAM.
(random access memory) and the like, and a write command is given to the storage unit 13. When the decoder 14 detects an end code indicating the end of one frame, it generates a one-pulse write end signal MI1. Furthermore, in the first storage unit 13, the frame data is taken out to the DAI bus, while the multiplexer 1
The read/write signal R/W1 supplied from R/W1 becomes the "1" level, and data for one frame is sequentially written. Corresponding to this read/write signal R/W1,
Address data is supplied to the multiplexer 15 via the address bus AB, and the write address of the first storage section 13 is designated by the multiplexer 15. The multiplexer 15 is further supplied with read address information from the address counter 16, and the address bus AB is controlled by the signal MPX2 from the status register 12.
Either the write address information supplied via the counter 16 or the read address information from the counter 16 is selected. The frame data read from the first storage section 13 is taken out to the DAO bus and supplied to the selector 17 and decoder 18. The decoder 18 detects an end code from the frame data read information, and generates a one-pulse read end signal MO1 in response to the detection of the end code. On the other hand, when the signal MPX1 supplied to the multiplexer 11 is at the "0" level, frame unit data is taken out to the DBI bus and the
The signal is supplied to a second storage unit 19 and a write end detection decoder 20, which are configured in the same manner as in the case of the DAI bus. The second storage unit 19 has the same capacity as the first storage unit 13, and has the same capacity as the multiplexer 1.
It is controlled by a read/write signal R/W 2 given by R/W 1 and addressed by output information from a multiplexer 21 . Write address information is supplied to this multiplexer 21 via address bus AB, and address counter 22
address information is supplied from the address information, and one of them is selected by the signal MPX3. The information read from the second storage section 19 is supplied to the selector 17 and the read end detection decoder 23 via the DBO bus. The selector 17 selects one of the frame data taken out to the DAO bus or the DBO bus according to the signal S, supplies it to a digital/analog converter (not shown), and outputs it as audio via a speaker. There is. The address counters 16 and 22 count address information when reading out the first and second storage sections 13 and 19, respectively, and are both supplied with a clock signal CLK for incrementing the count.
Then, the address counters 16 and 22 receive the signal
When CL1 and CL2 become "1", the contents of the respective counters are cleared and the count is incremented.The contents are cleared at the last address of the memory sections 13 and 19, and then the contents are cleared from the first address. It is designed to be counted in steps. In addition, the address counters 16 and 22 include
Preset signals L1 and L2 are respectively supplied,
When this signal L1 or L2 reaches the "1" level, the address of the counter 22 is changed to the counter 1.
6 or the contents of counter 16 to counter 2.
2, each is loaded, preset, and counted. Write or read end signals MI1, generated from the decoders 14, 18, 20, 23;
MO1, MI2, MO2 are status register 1
2 is supplied. This status register 1
2 consists of four flip-flops FI1, FO1, FI2, FO2 and a logic circuit (not shown) for latching the signals MI1, MO1, MI2, MO2. And 4 flip-flops FI1, FO1, FI
2. Depending on the storage state of FO2 and the generation of the end signal, the signals MPX1, MPX2,
It generates a command signal WAIT to stop the supply of MPX3, L1, L2, CL1, CL2, S and frame-by-frame data to the waveform data transfer device. ” to “9” are set. Then, as shown in Table 2, the level of each signal is determined and generated according to this state. In this case, flip-flop FI1, FO
1, FI2, and FO2 are all reset to "1".

【table】

【table】

[Table] Table 1 shows the four signals MI1 to MO2 and
The possible states of flip-flops FI1 to FO2 are listed. For example, state 1
is set when the flip-flop FI1 is set, that is, when writing to the first storage section 13 is completed, reading from the second storage section 19 is completed, and the signal MO2 is generated. State 2 is set when the flip-flop FO2 is "0", that is, when reading from the second storage section 19 is not completed and a write end signal for the first storage section 13 is generated. The settings below up to state 8 are as shown in the table. Note that state 1 also includes a case where signals MI1 and MO2 are generated simultaneously. Similarly, state 3 includes a case where signals MI2 and MO1 occur simultaneously. Furthermore, state 9 receives write and read end signals MI1, MI2, MO
Set when neither 1 nor MO2 is emitted. Also, in Table 2, the signal MPX1 is
Supply input data to the bus DAI in the “1” state,
MPX2 and MPX3 select data from address counters 16 and 22, respectively, in the state of "1". Further, when the signal S is "1", the bus DAO side is selected, and the data is read from the first storage section 13. In the frame buffer device configured in this manner, the first and second storage units 13 and 19 are alternately connected to each other via the multiplexer 11.
Frame worth of data is written. At the same time, data for one frame is read out alternately from the storage sections 13 and 19 that are not being written. In this case, for example, the first storage unit 13
If the timing of the end of writing to the second storage unit 19 coincides with the end of reading from the second storage unit 19, no problem will occur. However, for example, a case may occur in which writing to the second storage section 19 is not completed even though reading from the first storage section 13 has been completed. This will be referred to as case 1 below. Conversely, a case may occur in which writing to the second storage section 19 ends while the first storage section 13 is being read. This will be referred to as case 2 below. Even when reading and writing to the storage units 13 and 19 cannot be synchronized as in Cases 1 and 2, this frame buffer device is designed to operate sufficiently effectively. First, case 1 will be explained with reference to FIGS. 4 and 5. For example, at timing t ₁ the first
After writing to the storage unit 13 is completed, the second
It is assumed that the reading from the storage unit 19 of the two ends at the same time. Since this is state 1, the signal MPX generated from the status register 12
1, MPX2, .
9, data writing starts. Then, at timing _t2 , reading from the first storage section 13 is completed and the signal MO1 is generated. At this time, the second storage unit 19 is in the process of writing, so
Flip-flop FI2 is in the "0" state. In other words, this corresponds to state 8.
Note that between timing _t1 and _t2 , the end signals MI1,
Since none of MO1, MI2, and MO2 are generated, the state is state 9.
In state 8 at timing t ₂ , the signal
Since MPX2, S, and CL1 are at the "1" level,
The same frame data is read out from the first storage unit 13 again. Then, at timing _t3 , when writing to the second storage section 19 is completed, a signal MI2 is generated. At this time, signal MO1 has already been generated at timing _t2 , and flip-flop FO1 is set to "1".
Since it is in the latched state, it corresponds to state 7. In this state 7, writing to the first storage unit 13 is started.
Then, the signal L2 is sent to the second storage unit 19.
becomes "1", the contents of the address counter 16 are supplied to the address counter 22, the address information being read from the first storage section 13 is obtained, and the second
The reading of the storage unit 19 is started. That is,
One frame of data written in the second storage unit 19 is read from an address in the middle. Then, at timing _t4 , writing to, for example, the first storage unit 13 is completed, and at the same time, the writing to the second storage unit 13 is completed.
When reading from the storage unit 19 is completed, the state becomes state 1. In this way, in case 1, the first storage unit 13
When the data in the second storage section 19 is read out again and the writing to the second storage section 19 is completed, the read address information of the first storage section 13 is obtained and reading of the second storage section 19 is started, so that the data is output. This can prevent missing items. Further, case 2 will be explained with reference to FIGS. 6 and 7. For example, assume that at timing _t1 , writing to the first storage unit 13 ends, and reading to the second storage unit 19 ends at the same time. This is in state 1, in which reading of data in units of frames from the first storage unit 13 is started, and writing of data in units of frames to the second storage unit 19 is started. It is assumed that writing to the second storage section 19 is completed at timing _t2 while the first storage section 13 is being read. This state is the flip-flop FO
1 is "0" and the write end signal MI2 of the second storage section 19 is generated, so the state of state 4 is set. In this state 4, the signal WAIT goes to the "1" level and issues a command to inhibit frame-by-frame data transfer. Then, at timing _t3 , when reading of one frame of data from the first storage section 13 is completed, a read end signal MO1 is generated. In this case, since writing to the second storage unit 19 has already been completed, the flip-flop FI2 is set to "1". That is, the state of state 3 is set. In this state 3, the above signal
WAIT becomes “0” level, and the first storage unit 1
3 starts writing to the second storage unit 1.
Reading from 9 is started. Then, for example, at timing _t4 , if reading and writing are completed in agreement, the state becomes state 1. In this way, in case 2, if writing to the second storage section 19 is completed while the first storage section 13 is being read, a signal WAIT is generated to temporarily inhibit waveform data transfer. , when the reading of the first storage unit 13 is completed, the signal
I clear WAIT and synchronize. Incidentally, in cases 1 and 2, this also occurs when the first and second storage units 13 and 19 are just replaced, but it can be processed in the same way as above. In addition, in case 1, such a frame buffer device reads the data of the frame that has been output so far, and then outputs the data that should have been read from the middle of that frame. Information or image information works effectively because the data of adjacent frames are similar. As described above, according to the present invention, even if the input of frame-by-frame data cannot keep up with the output speed, it can compensate for it and output the frame-by-frame data from the output device without interruption. play.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a frame buffer device according to an embodiment of the present invention, FIG. 2 is a diagram showing the structure of data in units of frames supplied to the frame buffer device, and FIG. 3 is a diagram showing the structure of data in units of frames. FIGS. 4 to 7 are diagrams for explaining the contents of the data, and FIGS. 4 to 7 are diagrams for explaining the operation of the frame buffer device. 12...Status register, 13, 19...
First and second storage units, 14, 18, 20, 2
3... Decoder, 15, 21... Multiplexer, 16, 22... Address counter, 17...
selector.

Claims (1)

[Claims] 1. First and second storage means are provided, and when one of the storage means is performing a read operation, the other one is performing a write operation, thereby continuously inputting and outputting frame unit data. In a frame buffer device, when one of the first and second storage means has finished the read operation but the other has not finished the write operation, the beginning of the first and second storage means is a first control means for reading out the frame unit data from the address again; and, when the write operation of the other storage means is subsequently completed, a first control means for reading out the data in units of frames from the address; a second one for starting reading of the other storage means from the address;
1. A frame buffer device comprising: control means.