JPS6355746B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrostatic deflection circuit capable of obtaining extremely high electrostatic deflection voltages.

Compared to conventional methods, a high-energy ion beam is scanned and irradiated onto the surface of a solid sample to excavate the surface.
There is known an apparatus that analyzes the composition of a sample by stimulating sample ions released from the sample surface at this time. This type of device uses an electrostatic deflection circuit to deflect the ion beam. The high voltage sweep voltage generated by this electrostatic deflection circuit is applied to the electrostatic deflection electrodes to deflect the ion beam passing between the electrostatic deflection electrodes. By the way, in order to deflect a high-energy ion beam over a wide angle and with high precision, it is necessary to apply a high voltage to the electrostatic deflection electrode. Figure 1 is an electrical circuit diagram showing a conventional electrostatic deflection circuit for ion beams.
It consists of a pair of complementary voltage output circuits in which an NPN transistor and a PNP transistor are connected in series. In Figure 1, the NPN transistor
A circuit in which TR ₁ and PNP transistor TR ₂ are connected in series forms a first complementary voltage output circuit,
NPN transistor TR ₃ and PNP transistor TR ₄
A circuit in which these are connected in cascade forms a second complementary voltage output circuit. Deflection signals are input to input terminals 1 and 2 of these first and second complementary voltage output circuits, respectively.
e ₁ and e ₂ are given, and their output voltages are applied to the electrostatic deflection electrode 3. Therefore, the electrostatic deflection electrode 3 receives the differential voltage e ₃ between the first and second voltage output circuits.
will be added. FIG. 2 shows the timing of the deflection signals e ₁ and e ₂ and the voltage e ₃ applied to the electrostatic deflection electrode 3. In addition, +Vcc, - in Figure 1
Vcc indicates the power supply voltage.

Now, in a complementary voltage output circuit composed of an NPN transistor and a PNP transistor as shown in FIG. 1, the maximum output voltage is determined by the withstand voltage value of the PNP transistor. The reason is that in the case of NPN transistors, the withstand voltage is
This is because a voltage of about 1000V can be easily obtained, but in the case of a PNP transistor, a voltage withstand voltage of about 400V can only be obtained even at a high voltage. Therefore, when it is necessary to swing the deflection output in positive and negative directions, such as with the deflection output for scanning, it is only possible to obtain a deflection voltage of up to ±200V, and the conventional circuit shown in Figure 1 cannot accurately deflect a wide angle. I couldn't do it.

The present invention has been made in view of these points, and consists of connecting a voltage output circuit formed by cascading a plurality of NPN transistors in parallel to positive and negative power supplies, and driving the NPN transistors with an isolated amplifier that receives a deflection signal. A voltage of opposite polarity is generated at the output end of the voltage output circuit, and the difference voltage is applied to the electrostatic deflection electrode, so that a high voltage deflection output can be generated.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is an electrical circuit diagram showing an embodiment of the electrostatic deflection circuit for an ion beam according to the present invention (the same parts as in FIG. 1 are given the same reference numerals). In this figure, TR ₁₁ to _{TR 14} are NPN transistors, transistors TR ₁₁ and TR ₁₂ are connected in cascade to form a first voltage output circuit, and transistors TR ₁₃ and TR ₁₄ are connected in cascade to form a first voltage output circuit.
are connected in cascade to form a second voltage output circuit. D ₁ to _{D 4} are diodes inserted between the base and emitter to protect the transistors TR ₁₁ to TR ₁₄ , respectively.
This is to protect the emitter since it is the most vulnerable to reverse voltage between the emitters. A ₁ to _{A 4} are isolation amplifiers that receive a deflection signal e applied to the input terminal 10 and drive transistors TR ₁₁ to _{TR 14} with _an output signal isolated from the input signal _. Examples of the method include those using an isolation transformer and those using a photocoupler, but any method may be used as long as it insulates the input signal and outputs the signal as an output signal. Also, transistor
The reason why isolated amplifiers are used to drive TR ₁₁ to _{TR 14} is that bias adjustment of the drive circuit is easy, and transistors TR ₁₁ to
This is because the drive circuit has the advantage of not requiring a high withstand voltage since it can drive the TR ₁₄ . The isolation amplifiers A ₁ and A ₄ are configured to receive the deflection signal e at their negative input terminals (inverting input terminals), and the isolation amplifiers A ₂ and A ₃ are configured to receive the deflection signal e at their positive input terminals (non-inverting input terminals). ing. The output voltages of the first and second voltage output circuits are applied to the electrostatic deflection electrode 3, and a load resistor R is connected to the first and second voltage output circuits.

The operation of the embodiment of the present invention configured in this manner will be described next. A sawtooth deflection signal e is input to the input terminal 10.
When input, the transistors TR ₁₁ and TR ₁₄ become conductive during the positive half cycle of the deflection signal e, and current flows from the transistor TR ₁₁ through the load resistor R to the transistor TR ₁₄ . On the other hand, during the negative half cycle of the deflection signal e, transistors TR ₁₂ and TR ₁₃ conduct and current flows from transistor TR ₁₃ to the load resistor R.
through to transistor _TR12 . In this way, a current flows through the load resistor R depending on the polarity and magnitude of the input deflection signal e. Here, when transistors TR ₁₁ and TR ₁₄ or TR ₁₂ and TR ₁₃ are operating near the saturation point, the positive and negative power supply voltages ±Vcc
A voltage close to 1 is applied to the electrode portion of the electrostatic deflection electrode 3. By the way, since the withstand voltage of the NPN transistor is high as described above, it is easy to obtain a large amplitude deflection voltage of about ±1000V. Note that the insulation amplifiers A ₁ to _{A 4} have an insulation voltage of about 2000V, so they will not be destroyed.

Figure 4 shows a part of Figure 3 (part 1 surrounded by a broken line).
FIG. 3 is an electric circuit diagram showing a modification example in which the voltage resistance of 1) is further increased. This includes the circuit part consisting of the isolation amplifier A ₁ , the diode D ₁ and the transistor TR ₁₁ ,
Isolation amplifier A ₁ ′, diode D ₁ ′ and transistor
The circuit portions consisting of TR ₁₁ ′ are connected in cascade, and Zener diodes D ₁₁ and D ₁₁ ′ are further connected to protect the transistors TR ₁₁ and TR ₁₁ ′ from overvoltage. If the circuit shown in FIG. 4 is configured in a bridge shape as shown in FIG. 3, a deflection voltage twice as large as that shown in FIG. 3 can be obtained.

As explained above, according to the present invention, since the deflection voltage can be increased, deflection distortion is reduced, ion beam deflection with good linearity can be performed, and wide-angle ion beam scanning can be performed. . Furthermore, if necessary, the number of cascaded stages can be increased as shown in FIG. 4 or more to obtain a higher deflection voltage.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing a conventional electrostatic deflection circuit for ion beams, FIG. 2 is an explanatory diagram showing the timing of operation waveforms of the circuit in FIG. 1, and FIG. 3 is an electric circuit diagram showing a conventional electrostatic deflection circuit for ion beams. FIG. 4 is an electric circuit diagram showing one embodiment of the deflection circuit, and FIG. 4 is an electric circuit diagram showing a modification of the circuit of FIG. 3. 10...Input terminal, 3...Electrostatic deflection electrode,
TR ₁₁ ~ TR ₁₄ , TR ₁₁ ′...NPN transistor, D ₁
~ _D4 ...Diode, _D11 , _D11 '...Zener diode, _A1 ~ _A4 , _A1 '...Isolation amplifier, +Vcc,
-Vcc...Positive and negative power supply voltage.

Claims (1)

[Claims] 1. A voltage output circuit formed by cascading a plurality of NPN transistors is connected in parallel to positive and negative power supplies, and by driving the NPN transistor with an isolation amplifier that receives a deflection signal, the output terminals of the pair of voltage output circuits are An electrostatic deflection circuit characterized by generating polar voltages and applying the difference voltage to electrostatic deflection electrodes.