JPS6355802B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM demodulator that extracts a modulated signal component from a frequency modulated signal (hereinafter abbreviated as FM signal), and particularly relates to an FM demodulator suitable for IC implementation.

Conventionally, a phase detection type using a delay circuit has been widely used as an IC-based FM demodulation circuit. The phase detection type FM demodulation circuit has many advantages over other methods in terms of integrating the circuit into an IC. (1) The capacitance of the multivibrator used as a delay circuit is external to the IC. 2 pins for
Furthermore, in order to suppress variations in the maximum demodulation frequency fmax, one pin is required for a total of three pins.

(2) An adjustment circuit including a large capacitor outside the IC is required to adjust the playback output level.

There was a problem.

Figure 1 shows a conventional FM demodulation circuit, and Figure 2 shows the operating waveforms of each part.

In Figure 1, 1 and 2 are FM signal input terminals that directly input the limiter circuit output signal, 3 and 4 are pin terminals of the IC that connect the capacitor to the inside of the IC, 5 is an output voltage terminal that outputs the demodulated voltage, and 6 is the output voltage terminal that outputs the demodulated voltage. Pin terminals 7 to 3 that set the base potential of the current source inside the IC
0, 35 to 37, 41, 42 are all resistances, Q1
~Q23 are all transistors, C1 is an external capacitor, D1 to D4 are all diodes, 4
3 is an LPF, 38 is a variable resistor, Q40 is an external transistor, C2 is an external large capacity capacitor, and 39 is a video terminal. In FIGS. 2a to 2k, reference numerals 51 to 61 indicate operating waveforms of each part in FIG. 1.

The FM demodulation circuit shown in FIG. 1 will be explained below.

Limiter outputs as shown at 51 and 52 in FIGS. 2a and 2b are inputted from the FM signal input terminals 1 and 2 in FIG. 1. Note that 51 and 52 are in a relationship of opposite phases to each other. Here, the base potential of transistor Q15 is V _A , and the base potentials of Q24 and Q25 are
V _B is the base-emitter voltage of the transistor, V _BE
shall be. First, Q1, Q3 are OFF, Q2, Q4
Assume that C1 is ON and capacitor C1 is charged and in a steady state. At this time, transistor 3 is OFF and its collector potential becomes V _A - V _BE , so the emitter potential of Q4 (collector of Q2) is 5 in Figure 2 d.
As shown in Figure 4, V _A -3V _BE . Also, Q3
The emitter (collector of Q1) potential of Q3 is
Since it is OFF, it is determined by the emitter potential of Q4, and if the voltage across the capacitor C1 is ΔV, it becomes V _A −3 _BE +ΔV as shown at 53 in FIG. 2c.

Next, when t=t ₁ , when 51 and 52 are reversed, Q
1 is ON, Q2 is OFF, and the current is Q1,C
1, Q4, and the emitter potential 53 of Q3 is the second
It decreases linearly as shown in Figure c. At this time, Q
The collector potential of Q4 is clamped by Q24 and is V _B - V _BE , and the base potential of Q3 is V _B - V BE.
2V _BE . Therefore, when the discharge continues and the emitter potential 53 of Q3 reaches V _B -3V _BE , Q3 becomes
ON, and the discharge of capacitor C1 ends. Let this time be t= _t2 . At t=t ₂ , the moment Q3 turns ON, the base potential of Q4 drops to V _B -2V _BE and Q4
is turned off. The circuit shown in Figure 1 is a completely symmetrical circuit, so Q1 and Q3 are ON, and Q2 and Q4 are ON.
The state at the time of OFF is the same as replacing the state of t≦t ₁ of the waveforms 53 and 54 in FIGS. 2c and d with 53 and 54. In other words, the emitter potential of Q3 is V _A -3V _BE and the emitter potential of Q4 is V _A -3V _BE +
It becomes ΔV.

Furthermore, at t= _t3 , when 51 and 52 in FIG. 2 a and b are reversed again, and Q1 is turned OFF and Q2 is turned ON, the current flows through Q2, C1, and Q3 and is discharged.

As described above, the FM demodulation circuit shown in FIG. 1 repeats the above-mentioned operation every cycle, and
Operating waveforms such as b, c, and d are shown.

By the way, the voltage ΔV across the capacitor C1 in a steady state is the emitter potential difference between the transistors Q3 and Q4 just before they switch at t= _t2 , so ΔV=V _A −3V _BE −(V _B −3V _BE )=V It becomes _A −V _B. Therefore, the potential difference between the capacitor before it starts discharging and when it ends is V _A −3V _BE +ΔV−(V _B −3V _BE )=2ΔV.

Next, the emitter potentials of transistors Q5 and Q6 can be determined by paying attention to the states of Q3 and Q4.
This results in signal waveforms such as 55 and 56 shown in f, which means that these are delayed with respect to the input signals 51 and 52. The delayed signal is multiplied by the input signal in the next multiplication circuit, and the collector potentials of Q7, Q8, Q9, and Q10 are 57 to 57 as shown in g, h, i, and j in FIG.
The signal waveform will be like 60. Furthermore, output terminal 5
If load resistor 40 is connected to terminal 5, Q12 is connected to terminal 5.
Or current flows only when Q13 is ON,
61 signals shown in FIG. 2k are output. That is, the base potential of Q11 to Q14 (Q7 to Q10
Only when Q12 or Q13 is kept at the highest potential (collector potential of
During other periods, the voltage is always maintained at the power supply voltage. In other words, if the current is I ₀ and the load resistance is R _L , the discharge period (delay period) decreases to V _CC −R _L I ₀ , and in other periods
Repeat 61 waveforms to reach the V _CC state.
By the way, since the discharge changes linearly as shown in Figure 2, the discharge time, that is, the delay time τd (τ=t ₂ − _{t 1} )
If the capacitance of the capacitor C1 is C and the current of the constant current source is I _D , then it becomes as follows.

τd=2C・ΔV/I _D …(1) Furthermore, the average value of the output voltage 61 of terminal 5 is the input
If the period of the FM signal is T, then V _DC =V _CC -4ΔV·R _L C/T×I ₀ /I _D (2), and the second term is proportional to the frequency f=1/T of the FM signal. Figure 7 shows the average output voltage of terminal 5 and
Shows the relationship with the frequency of the FM signal. As shown in FIG. 7, the output voltage changes linearly from V _CC to V _CC -I ₀ R _L , and reaches its minimum at the maximum demodulation frequency fmax.

As described above, with the circuit configuration shown in Figure 1,
Although it is possible to realize an FM demodulation circuit, (1) 2 pins are required as terminals for using external capacitors, and 1 pin is required to suppress the influence of variations in demodulation characteristics caused by variations in internal resistance of the IC, resulting in a total of 3 pins. A pin is required.

(2) It is necessary to adjust the playback output level using an adjustment circuit outside the IC, which results in a circuit configuration that includes a large capacitor, and the large capacitor does not allow quick adjustment.

There was a problem. These problems are a major problem as ICs become more multi-functional, highly integrated, and lower in price.

The purpose of the present invention is to eliminate the above-mentioned conventional drawbacks, reduce the number of pins by 1 pin, suppress the effects of variations within the IC, and achieve a miniaturized circuit as well as low cost and low power consumption. The object of the present invention is to provide a demodulation circuit.

In the present invention, the capacity of the multivibrator is
Reduce the number of pins by incorporating it internally.
Furthermore, by independently performing demodulation sensitivity adjustment and demodulation output level adjustment using resistors outside the IC, the effects of variations in capacitance and resistance within the IC are suppressed.

An embodiment of the present invention will be described below with reference to FIG.

The difference between FIG. 3 and FIG. 1 is that the capacitor C1, which was external in FIG. , the resistor 33 and the external variable resistor 44 connected to the pin terminal 40, and the base potential of the current source transistor Q20 is supplied from the transistor Q.
26, a resistor 32, and an external variable resistor 35 connected to the pin terminal 41.

The circuit operation in FIG. 3 is similar to that described in FIG. As explained in FIG. 1, the delay time τd due to the delay circuit is calculated as follows: τd is the capacitance of the capacitor C1, I _D is the current of the constant current source consisting of the transistor Q17 and the resistor 21, and ΔV is the charging voltage of the capacitor. =2CΔV/ _ID ...(1). In addition, the average value of the output voltage of terminal 5 is determined by the current of the constant current source consisting of transistor Q20 and resistor 28, where R _L is the load resistance connected to terminal 5.
I ₀ and the period of the input FM signal is T, then V _DC =V _CC -4ΔVR _LC /T×I ₀ /I _D (2).

The number of pins can be reduced by incorporating a capacitor inside the IC, but there is a problem with the variation in built-in capacitors. That is, by incorporating the capacitor C1, a large variation of about ±30% must be allowed.
As can be seen from equations (1) and (2), variations in capacitance are directly related to variations in demodulated voltage. In Figure 1, if only the capacitor C1 is built-in, the variation in the capacitor C1 of ±30% will cause a variation in the demodulated voltage.
Adjustment must be performed using a circuit including a large capacitance C2 outside the IC, which is extremely difficult.

Therefore, in order to suppress variations in the demodulated voltage, the delay time τd can be adjusted using an external resistor. In other words, the variation in capacitance C is expressed as constant current source current.
This is absorbed by adjusting the _ID . In a specific embodiment of the present invention, the base of the constant current source transistor Q17 of the delay circuit is connected to the transistor Q in FIG.
27, a resistor 33, and a load resistor connected to a pin terminal 40. Here, the use of an external load resistor has the effect of not only absorbing variations in capacitance C through adjustment, but also making the resistance accuracy ±5% and suppressing variations due to resistance. As described above, according to the present invention, variations in capacitance C can be absorbed, variations in internal resistance can be absorbed by adjustment with external resistors, and delay time τd can be set regardless of the variations.

Furthermore, as another method for suppressing variations in the demodulated voltage, it is also possible to adjust the current flowing to the demodulated output pin terminal 5 using an external resistor.
That is, as can be seen from equation (2), variations in the capacitance C are absorbed by adjusting the constant current source current _I0 . A specific embodiment of the present invention is to supply the base potential of the constant current source transistor Q20 of the output stage of the multiplication circuit shown in FIG. It is. According to the present invention, similar to the above-mentioned adjustment, there is an effect of suppressing variations and stabilizing the reproduction output level. Of course, as can be seen from equation (2), I ₀ and _ID can be adjusted not only to absorb variations in capacitance, but also to mutually absorb variations in current due to variations in resistance. The adjustment will now be explained using FIG. 7. First, adjustment of I _D involves adjusting τ from equation (1). Adjusting τ is fmax in Figure 7.
Only the frequency of fmax will be changed while keeping the voltage at V _CC −I ₀ R _L. Therefore, the demodulation characteristic is as shown by the dotted line 201 in FIG. 7, and the demodulation sensitivity can be changed and the demodulation voltage can be adjusted to suppress variations.

Next, adjustment of I ₀ means changing only the output voltage at fmax without changing the maximum demodulation frequency fmax in FIG. 7 from equation (2). Therefore, the demodulation characteristic is as shown by the dashed line 202 in FIG. 7, and the demodulation sensitivity can also be changed and the demodulation voltage can be adjusted to suppress variations.

To summarize this embodiment described above, it has the following features.

(1) The number of pins according to the present invention (1 pin for maximum demodulation frequency adjustment, 1 pin for adjusting the maximum demodulation frequency,
(1 pin for maximum demodulation voltage adjustment) 2 pins and 1 pin can be reduced.

(2) Adjustment of the playback output level can be achieved by changing the currents I ₀ and _ID within the IC, eliminating the need for an adjustment circuit including a conventionally used large-capacity capacitor.

Among the above features, (1) reduction in the number of pins is the most effective in increasing the integration and multifunction of ICs. In addition, (2) adjusting the reproduction output level by adjusting the resistor directly connected to the IC pin can minimize variations in the demodulation circuit in a short time, and is the most effective adjustment for the built-in capacitor type. Figure 4 shows an example in which the feature (2) can be utilized more effectively.
FIG. 4 is a block diagram of a so-called line correlation circuit and video dropout compensation circuit having two demodulation circuits in the system. In FIG. 4, 51 is a reproduced FM signal input terminal, 52 is an FM dropout compensation switch, 53 is a delay line, 54 is a limiter, 55 is a first demodulation circuit, 56 is an adder;
7 is a video dropout compensation switch, 58 is a limiter, 59 is a second demodulation circuit, 60 is a subtracter,
61 is a limiter, 62 is a video signal output terminal, 63
64 is a dropout signal input terminal, and 64 is a pulse delay circuit. Since the circuit configuration shown in FIG. 4 is well known, its explanation will be omitted. The present invention concerns the characteristics of the first demodulation circuit and the second demodulation circuit. In other words, what is required of the two demodulation circuits in FIG. 4 is not only sufficient individual demodulation characteristics, but also symmetry between the two. Variations in the two demodulation characteristics have a large effect on the system shown in FIG. Therefore, in order to achieve symmetry in the demodulation characteristics, the maximum demodulation frequency adjustment resistor 44 and the maximum demodulation voltage adjustment resistor 35 shown in the embodiment of the present invention in FIG.
Make adjustments according to In order to adjust the two demodulation circuits in a system like the one shown in Figure 4,
First, there is a method in which both maximum demodulation frequencies are matched and then the maximum demodulation voltage is adjusted. Conversely, there is a method in which the maximum demodulation voltage is matched and then the maximum demodulation frequency is adjusted. However, in order to improve adjustment efficiency, the above method is time-consuming and impractical. Therefore, first allow the maximum demodulation voltage within the range of variation, and then set the maximum demodulation frequency adjustment resistor 44.
The most efficient adjustment method is to adjust only with A and 44B, or conversely, allow the maximum demodulation frequency and adjust with maximum demodulation voltage adjustment resistors 35A and 35B. Furthermore, it is also possible to adjust 44A and 44B together from one adjustment pin, and to adjust 35A and 35B together.
Of course, even in the case where only one is used instead of using two as described above, adjusting both the maximum demodulation frequency and the maximum demodulation voltage is a problem in terms of efficiency improvement.
Therefore, similarly to the above method, it can be said that a method of adjusting only the maximum demodulation frequency, or conversely a method of adjusting only the maximum demodulation voltage, is an efficient method.

FIG. 5 shows another embodiment of the invention. The difference between Fig. 5 and Fig. 3 is that the transistor Q15 is removed, the emitters of Q5 and Q6 are clamped by Q24 and Q25, and the collectors of Q3 and Q4 are
The reason is that diodes Q31 and Q32 are provided from V _CC . This is configured so that it can be used with V _CC lower than that of the embodiment shown in FIG. 3, thereby realizing lower power consumption, and is essentially the same as the circuit operation shown in FIG. 1. In Fig. 5, capacitor C1 is also
Built into the IC, pins 40 and 41 are used to adjust variations.
is taken out of the IC to keep the playback output level constant.

In this example, if the potentials of input terminals 1 and 2 and the voltages across resistor 8 are V ₁ and V ₂ respectively, the power supply voltage V _CC is V _CC = V ₁ + 2V _BE + V ₂ , and V ₁ = 2V, V If _BE = 0.7V, V ₂ = 0.7V, V _CC = 4.1V, and the power supply voltage should be adjusted with a margin.
Can be set to 4.5V.

FIG. 6 shows another embodiment of the invention. In Fig. 6, 101 and 102 are FM signal input terminals, 10
3 is a demodulation output terminal, 104 is a reproduction output level adjustment terminal, 110 to 119 are all resistors, 120 to 1
22 is a constant current source, Q131 to Q147 are transistors, D148 and D149 are diodes, and C1 is a capacitor.

C1 in FIGS. 3, 5, and 6 is composed of a MOS capacitor. As described in Japanese Patent Application No. 56-98244, the MOS capacitor has a metal side electrode and a substrate side electrode, and has a large stray capacitance between the substrate electrode and ground. For example, if the above-mentioned stray capacitance is added only between the emitter of Q3 in Figure 3 and the ground, the carrier leakage characteristics will deteriorate, so to prevent this, Q4
It is necessary to take measures to create the above stray capacitance between the emitter and ground. For example, in Figure 6, C1 is configured with two MOS capacitors, and the first MOS
The metal side electrode of the capacitor is connected to the collector of Q142, the substrate side electrode is connected to the collector of Q143, and the metal side electrode of the second MOS capacitor is connected to the collector of Q142.
Connect the substrate side electrode to the collector of Q1.
It is sufficient to connect each of the 42 collectors.

Although FIG. 6 has a different configuration from FIGS. 3 and 5, the essential circuit operation is the same. Here, if the capacitance of the capacitor is C, the voltage applied across the capacitor is ΔV, and the current of the constant current source is I, the delay time τd becomes τd=2ΔV·C/I (3). Further, if the output load resistance of the terminal 103 is R, the average value V ₀ of the output voltage of the terminal 112 is V ₀ =IR-4ΔV·RC/T (4). Therefore, as can be seen from equation (4), even in the circuit configuration of FIG. 6, the variation due to the internal capacitor is adjusted using the adjustment terminal 104, and by suppressing the variation, the reproduced output level is made constant.

According to the present invention, the conventional external capacitor can be replaced with
By incorporating it inside the IC, the number of pins can be reduced by one from the conventional pin count. At the same time, a pin for adjusting the maximum demodulation frequency and a pin for adjusting the maximum demodulation voltage can be provided, which has the effect of making the IC smaller, more functional, and lower in price.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of a conventional example, Fig. 2 is a diagram showing operating signal waveforms of the conventional example, Fig. 3 is a diagram showing an embodiment of the present invention, and Fig. 4 is a diagram showing the line correlation of the present invention. 5 is a diagram illustrating an example of application to a video DOC circuit; FIG. 5 is a diagram showing another embodiment of the present invention; FIG.
This figure shows another embodiment of the present invention, and FIG. 7 is a diagram showing the relationship between output voltage and frequency. 1, 2...Reproduction FM signal input terminal, 5...Demodulation output terminal, C1...Capacitor, 40...Maximum demodulation frequency adjustment pin, 41...Maximum demodulation voltage adjustment pin.

Claims (1)

[Claims] 1. In an FM demodulation circuit comprising a delay circuit that delays an input signal and a multiplier that receives the input signal and the output of the delay circuit as input, an emitter capacitively coupled multivibrator used as the delay circuit. The capacitor is built into the IC, and the base potential of the constant current source transistor for adjusting the current flowing to the multiplier is connected to the first transistor in the integrated circuit.
The current flowing through the delay circuit and the current flowing through the multiplier can be adjusted independently by supplying the current from a circuit consisting of a resistor and an external resistor connected to a pin terminal of the integrated circuit. FM demodulation circuit featuring: 2. The base potential of the constant current source transistor for adjusting the current flowing through the delay circuit is determined from a circuit consisting of a second transistor in the integrated circuit, a second resistor, and an external resistor connected to a pin terminal of the integrated circuit. 2. The FM demodulation circuit according to claim 1, wherein the FM demodulation circuit is configured to supply an FM demodulation circuit.