JPS6356505B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a semiconductor device, and more particularly, to an open drain output test method for a semiconductor device.
The present invention relates to a method for measuring characteristics of MOS transistors.

A method for measuring the characteristics of a conventional open-drain output MOS transistor in a semiconductor device will be explained with reference to FIG. In FIG. 1, 1 is an open-drain output P-channel MOS transistor, whose gate is connected to an input terminal 2 to which internal signals of the semiconductor device are applied, whose source is connected to a power supply terminal 3, and whose drain is connected to an input terminal 2 to which internal signals of the semiconductor device are applied. Connected to output terminal 4. 5 is an external resistor connected between the drain of the MOS transistor 1 and ground.

In this way, conventionally, open-drain output
With an external resistor 5 as a load connected between the drain of the MOS transistor 1 and the ground, an input signal as shown in Fig. 2A is applied to the input terminal 2.
By operating the MOS transistor 1, obtaining a negative signal (output signal) of the input signal at the output terminal 4, and measuring the signal waveform (output waveform) with an automatic test device, the open drain output
Characteristics of MOS transistor 1 were measured.

At this time, an external load capacitor 6 such as a capacitor of an output monitor terminal of an automatic test device is connected between the drain of the MOS transistor 1 and the ground as shown in FIG. Therefore, for the output waveform in the circuit shown in FIG. As the value (resistance value×capacitance value) increases, the output waveform shifts from FIG. 2B to FIG. 2C.

The output monitor terminals of typical automatic test equipment typically have a fairly large capacitance. Therefore, the fall of the output waveform becomes slow as shown in FIG. 2B and C. To speed up the fall time, use external resistor 5.
must be made smaller. However, if the external resistor 5 is made small, the drain current becomes excessive when the MOS transistor 1 becomes conductive, and the high value output level decreases, making it impossible to obtain a normal high value level.

In this way, in the conventional method, the fall of the output waveform becomes slow due to the influence of the external load capacitance 6, and on the other hand, when the fall time is made faster by decreasing the external resistance 5, a normal high value level cannot be obtained. . Therefore, from the output waveform, the open drain output
It was not possible to accurately measure the characteristics of the MOS transistor 1.

The present invention was made in view of the above points, and an object of the present invention is to provide a semiconductor device testing method that can reduce the influence of external load capacitance and accurately measure the characteristics of an open-drain output MOS transistor. do.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a circuit diagram for explaining one embodiment of the present invention. In this figure, 11 is an open-drain output P-channel MOS transistor, whose gate is connected to an input terminal 12 to which an internal signal of the semiconductor device is applied, whose source is connected to a power supply terminal 13, and whose drain is an output terminal. 14
connected to. Reference numeral 15 denotes an N-channel MOS transistor provided according to the present invention, and its gate is connected to the input terminal 12, its drain is connected to the second output terminal 16, and its source is grounded. 17 is a P channel MOS transistor 11
is the external load capacitance connected between the drain and ground.

In such an embodiment, when measuring the characteristics of the open-drain output P-channel MOS transistor 11, the output terminal 14 and the second output terminal 16 are shorted and a load is applied to the drain side of the P-channel MOS transistor 11. N channel as
MOS transistors 15 are connected in series. Then, an input signal as shown in FIG. 2A is applied to the input terminal 12.

Now, when the low level of the input signal is applied to the input terminal 12, the P channel MOS transistor 1
1 is conductive, the N-channel MOS transistor 15 is cut off, and the output terminal 14 (output waveform) becomes a high level. At this time, the external load capacitor 17 is charged by the drain current of the P-channel MOS transistor 11. Also, at this time, as mentioned above, the N-channel MOS transistor 15 is in the cutoff state and corresponds to an infinite resistance, so the high level of the output terminal 14 is a normal high level close to the voltage of the power supply terminal 13. .

Next, when the high level of the input signal is applied to the input terminal 12, the P channel MOS transistor 1
1 is cut off, the N-channel MOS transistor 15 is turned on, and the output terminal 14 (output waveform) is at the resistance level. At this time, the charge on the external load capacitor 17 is discharged through the N-channel MOS transistor 15. The N-channel MOS transistor 15 has an on-resistance equivalent to a small resistance from a transient state in which the level of the output terminal 14 changes from a high value to a low value to a stable state. Therefore, the time constant for discharging the charge stored in the external load capacitor 17 is small. As a result, the speed at which the level of the output terminal 14 changes from a high value to a low value (fall time of the output waveform) is fast.

Note that when the output terminal 14 and the second output terminal 16 are short-circuited, a complementary configuration is established, so that when the input signal transitions from a high value to a low value or from a low value to a high value, the drain is connected to the MOS transistor 11 or 15. Only current flows; when stable, no current flows.

In addition, when operating as an actual semiconductor device, by separating the output terminal 14 and the second output terminal 16, the P-channel MOS transistor 1
1 can be operated as an open drain output circuit without any problem in electrical characteristics.

As described above, according to one embodiment, the influence of the external load capacitance 17 can be reduced, the fall time of the output waveform can be made faster, and a normal high value level can be obtained. Therefore, from this output waveform, the P channel of open drain output
The characteristics of the MOS transistor 11 can be measured with high accuracy.

Note that the above embodiment has an open drain output.
Although the case where the MOS transistor is a P channel is shown, when the MOS transistor is an N channel, the N channel MOS transistor 15 in Fig. 3 is used.
By connecting a P-channel MOS transistor in the same manner instead, it is possible to measure the characteristics of an open-drain output N-channel MOS transistor in the same manner as in the first embodiment. In that case as well, it goes without saying that the same effects as in the embodiment can be obtained. However, open drain output
Conventionally, when the MOS transistor is N-channel,
The rising speed of the output waveform was slow due to the influence of the external load capacity. By connecting a P-channel MOS transistor as a load to the drain side of the open-drain output N-channel MOS transistor, the rise time of the output waveform can be made faster.

As detailed above, in the semiconductor device testing method of the present invention, a MOS transistor of the opposite channel having a common input with the open-drain output MOS transistor is connected to the drain side of the open-drain output MOS transistor as a load. , it is possible to accurately measure the characteristics of open-drain output MOS transistors by reducing the influence of external load capacitance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining a conventional method for measuring characteristics of an open-drain output MOS transistor, FIG. 2 is an input/output waveform diagram for the circuit shown in FIG. 1, and FIG. 3 is a test method for a semiconductor device according to the present invention. FIG. 2 is a circuit diagram for explaining one embodiment of the present invention. 11...Open drain output P channel
MOS transistor, 15...N channel MOS transistor, 17...external load capacitance.

Claims (1)

[Claims] 1 Connect a load to the drain side of the open-drain output MOS transistor, operate the open-drain output MOS transistor in that state, and determine the open-drain output MOS from the output waveform at that time.
1. A semiconductor device testing method for measuring characteristics of a transistor, characterized in that a MOS transistor of an opposite channel having a common input to the open drain output MOS transistor is used as the load.