JPS6356548B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a scanning method for moving a window (rectangle) specified by the coordinates of two points in a bit map memory corresponding to a set of bright spots on a display screen. Regarding the window movement control method in which a fixed bit length N in the line direction is used as a unit, in particular, processing of the remainder of the fixed length N that occurs at the start and end ends of the window in the scanning line direction is adjusted using a shift circuit, and This invention relates to a window movement control system on a bit map memory in which the original data is guaranteed by executing read-modify-write when writing a remainder to a fixed length N.

[Conventional technology and problems]

A bit map memory corresponding to a set of bright spots on a display screen is normally read and written using a fixed bit length N (for example, 8 bits, 16 bits, etc.) in the scanning line direction as an access unit. Conventionally, moving windows on bit map memory has been done using a program or a bit map memory.
This was done using hardware that was limited to map memory access units.

However, when moving a window on the bit map memory by a program, all the data in the window is read in each access unit, the remaining data for the fixed length N at the start and end is shifted and repacked, and then written again. Processing is performed by inserting the original data that should be guaranteed at the beginning and end, and then writing. Therefore, there are disadvantages in that the amount of processing increases and the processing speed becomes slow.

In addition, when moving the bit map memory window using hardware limited to the latter bit map memory access unit,
Since the window can only be moved within a range consistent with the access unit, there is a boundary of the bit map memory access unit, which has the disadvantage that window movement is restricted.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks, and allows a window composed of a free bit length to be moved to an arbitrary position at high speed without being restricted by the access unit of the bit map memory. The object of the present invention is to provide a window movement control method on a bit map memory that can perform the following steps.

[Structure of the invention]

For this purpose, the window movement control method on the bit map memory of the present invention
Move the window specified by the coordinates of two points on the memory to another rectangular area on the bit map memory specified by the coordinates of the two points by accessing it in units of fixed bit length N in the scanning line direction. Bits to do
A window movement control method on a map memory, comprising a temporary storage means for reading and storing data in the above unit sequentially from the read-out head address of the window, and a predetermined number of bits of the data stored in the temporary storage means. Shifting means for shifting and outputting each bit length of the above unit; selecting either the data output by the shifting means or the data read from the write address of the rectangular portion in accordance with the above unit; and writing at the write address. The above bits as data
comprising at least data selection means for sending to the map memory and control means for overall control;
The control means determines the number of shift bits in the shift means based on the difference between the remainder of the read start address with respect to the bit length N and the remainder of the write start address with respect to the bit length N, and when writing the start end, Based on the remainder of the bit length N of the address, the data to be selected by the data selection means is determined so that the original data at the front side of the write address is guaranteed, and when writing the end, the bits at the write end address are selected. The shift means and the data selection means are controlled to determine the data to be selected by the selection means so that the original data at the rear of the write address is guaranteed based on the remainder with respect to the length N. It is characterized by this.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of a window and movement destination specified by the coordinates of two points, and FIG. 3 is a diagram showing data shift and read modification. - It is a diagram showing an outline of the light.

In FIG. 1, 1 is a bit map memory, 2 is a read address register, 3 is a write address register, 4 is a write end address register, 5 is a comparator, 6 is a subtracter, 7 is a temporary storage register, and 8 is a shifter. , 9 is the start gate, 10 is the end gate, 11
is a control ROM, 12 is a control circuit, 13 and 14 are multiplexers, a is a remainder for the fixed length N of the read start address, c is a remainder for the fixed length N of the write start address, d is a remainder for the fixed length N of the write end address The remainder, X _C is the write start address, X _D is the write end address,
is a match signal, is a memory signal, is a shift signal,
Indicates the start/end gate signal, the difference signal, and the start/end notification signal. Further, in FIG. 2, 15 is a bit map display, A (x _A , y _A ) is a reading start address, B (x _B , y _B ) is a reading end address,
C (x _C , y _C ) is the write start address, D (x _D , y _D ) is the write end address, and X _A , X _B , X _C , and X _D are the access addresses.

As shown in FIG. 2, the present invention allows a window to be opened, for example, on the bit map display 15 by a reading start address A (x _A , y _A ) and a reading end address B (x _B , y _B ). specified, and if you want to move it to another rectangular area specified by the write start address C (x _C , y _C ) and the write end address D (x _D , y _D ), access the constant length N. The bit length of the window, the start address, the end address, etc. can be freely set as a unit, and FIG. 1 shows an example of this. In FIG. 1, the read address of the window is set in the read address register 2, the write address of the destination area is set in the write address register 3, and the write end address of the destination area is set in the write end address register 4. Ru. The comparator 5 compares the write start address _XC and the write end address _XD , and if they match (described later with reference to FIGS. 9 and 10), a match signal is sent to the control circuit 12. Ru. On the other hand, the subtracter 6 subtracts the remainder C for the constant length N of the write start address and the remainder a for the constant length N of the read start address, and sends the difference signal to the control circuit 12. As will be detailed later, the control circuit 12 receives the match signal from the comparator 5 and the difference signal from the subtracter 6, sends a storage signal to the temporary storage register 7, and sends the storage signal to the shifter 8.
A shift signal is sent to the control ROM 11, and a start/end notification signal is sent to the control ROM 11. Other control circuit 12
is the one that controls the whole. In the temporary storage register 7, data of fixed length N is read out from the window of the bit map memory 1 in accordance with the access unit, and 2N data is stored. shifter 8
determines the shift number to match the write start address based on the difference between the remainder a for the constant length N of the read start address and the remainder C for the constant length N of the write start address, and stores the write data from the temporary storage register 7. As a result, output data of a constant length N is obtained.
The output data of the constant length N of the shifter 8 is written to the write address of the bit map memory 1 through the multiplexer 14.
The start and end gate signals read from the ROM 11 control the start and end gates 9 and 10 of the multiplexer 14, and the data at the write address in the bit map memory 1 is read, modified, and written. The control ROM 11 uses the remainder C for the fixed length N of the write start address and the remainder d for the fixed length N of the write end address as addresses based on the start/end notification signal of the control circuit 12, and performs a read that guarantees the original data. - Start and end gate signals for gate operation for modify write are read out.

Data Shift and Read Modification
Figure 3 shows an overview of the light. In FIG. 3, 8' is a shifter mechanism, 7-1 and 7-2 are temporary storage registers, 8 is a shifter, R/M/W is a read/modify/write gate,
The dotted line indicates the shift range (width 2N-1). Figure 3A is from the reading start address x _A to the reading end address x _B
This indicates that the shaded area up to is read out and written to the shaded area from the write start address _xC to the write end address _xD through the shifter mechanism 8', and the width of the vertical line is a constant length N in access units. be. Figure 3B is a
>c, the read data is sequentially set from temporary storage register 7-1 to 7-2 by fixed length N, and the difference (a- Data of constant length N shifted by c) is output from the shifter 8. The first part c is the read/modify/write gate R/ to guarantee the original data.
M/W is controlled. Also, in the start end processing when a≦c, although not shown, the data at the read start address x _A is stored in the temporary storage register 7 according to the access unit.
-1. and temporary memory register 7
The shifter 8 outputs constant length data shifted by the difference (N+ac) from the beginning of -2. By using such a shift number, read and write operations are matched. Thereafter, data is set in the temporary storage register 7-1 according to the access unit, and at the same time, the data in the temporary storage register 7-1 is shifted to the temporary storage register 7-2, and each time the data is shifted from the shifter 8 to the above-mentioned shift number. The data to be written to the write address is sent out according to the following. During this time, there is no need to guarantee the original data, so no read/modify/write is performed. FIG. 3C shows an outline of the termination process. As a result of the shift number of the shifter 8 being fixed at the start end as _{shown in FIG. 3B, the data at the read end address x B is} set to be written to the write end address The remainder d with respect to the constant length N of _D must be read to ensure the original data.
Modify write gates R/M/W are controlled.

FIG. 4 is a diagram showing a specific embodiment of the present invention including a CRT display. In FIG. 4, 1 to 3, 6 to 8, 11 and 13 to 15 indicate those corresponding to FIGS. 1 and 2, 16 is a multiplexer, 17 is a memory address register, 18 is a display counter, 19 indicates a shift register. In FIG. 4, input data and output data can be read and written to the bit map memory 1 by instructions using a memory address from an external device (for example, a central processing unit). In addition, the bit map memory 1 uses the display counter 18 as an address to display on the CRT display 15.
The read data is parallel-to-serial converted by a shift register 19 and sent to a CRT display 15 as a video input. However, in the case of window movement according to the present invention, a read address and a write address are designated and set in the read address register 2 and the write address register 3. The read data is temporarily stored in the temporary storage registers 7-1 and 7-2, and the number of shifts of the shifter 8 is determined as described above with reference to FIG. Output. At the start end, the data at the start end write address is read out, and the multiplexer 14 performs bit-by-bit switching between the output data of the shifter 8 and the data at the start end write address by the output of the control ROM 11 with C as the address. Necessary bit data of the original data at the write address is combined with the output data. By writing the output data of the multiplexer 14, the processing at the start end is completed. From then on, the output data of the shifter 8 is written as is until the end processing is performed, and the read/write is performed at the end in the same way as at the beginning.
Executing the modify write is as described above.

FIGS. 5 and 6 are diagrams showing specific configuration examples of the temporary storage register and the shifter section. In the figures, 6 to 8 indicate those corresponding to FIGS. 1 and 4, 8-00 to 8-OF, 8-E0
8-EF and 8-F0 to 8-FF represent AND gates, and 8-0 to 8-F represent OR gates. FIG. 5 shows a case where the constant length N is 16, and the data read from the window of bit map memory 1 is first read out from the temporary storage register 7.
-1, then temporary storage register 7-2
is memorized. The subtracter 6 calculates the remainder a for the constant length 16(N) of the read start address and the remainder c for the constant length 16(N) of the write start address,
This is an ALU that outputs 16 (N) answers. Then, the output of 4 bits (16 bits when decoded) is sent from the subtracter 6 to the shifter 8. shifter 8
For example, when is selected, data from bit 0 to bit 15 of temporary storage register 7-1 is output, and when is selected, data from temporary storage register 7-2 is output.
The data from bits 8 to 15 of the temporary storage register 7-1 and the data from bits 0 to bit 7 of the temporary storage register 7-1 are output. FIG. 6 shows an example in which the shifter 8 is composed of an AND gate and an OR gate. The subtracter 6 has output terminals ranging from 1 to 0, and is configured such that only one output terminal becomes logic "1" depending on the result of the operation. Shifter 8 is an AND gate 8-F0 to 8-FF
The group is bit 0 of temporary storage register 7-1.
The data of bits 1 to 15 are used as one input, and the outputs 1 to 0 of the subtracter 6 are respectively used as the other input. Furthermore, AND gate 8-E0 to 8-EF
A group of
The group of 0 to 8-FF is shifted by 1 bit and used as one input, and the output of the subtracter is 1 to 1.
6 as the other input. Similarly, and
1 for groups from gate 8-00 to 8-0F
Six groups of AND gates are provided, and the output of each group of AND gates is provided to OR gates 8-0 through 8-F. Therefore, for example, when the output terminal 1 of the subtracter 6 is logic "1", the AND gates 8-F0, 8-E0...
...The data input to 8-00, that is, the data from bit 1 to bit 15 of temporary storage register 7-2 and the data from bit 0 of temporary storage register 7-1 are OR gates 8-0 to 8-F. is output through.

FIG. 7 is a diagram showing an example of the configuration of the multiplexer 14, and FIG. 8 is a diagram showing an example of the configuration of the control ROM 11. In Figure 7, 14-10 to 14
-1F and 14-20 or 14-2F are and.
Gates 14-30 to 14-3F indicate OR gates and constitute the multiplexer 14. AND GATE 14-10 to 14-1F
The shifter from shifter 8 is connected to one input terminal of
Out data is supplied and AND gate 14
-20 to 14-2F one input terminal,
Read out from bit map memory 1
Data is supplied. And Gate 14
-10 to 14-1F and the other input terminal (inverting input terminal) of AND gates 10-20 to 14-2F are connected to the control ROM1.
Starting and ending terminal gate signals from 1 are supplied. The output terminals of AND gates 14-10 and 14-20 are connected to the input terminal of OR gate 14-30, and similarly AND gates 14-1F and 14-2 are connected to the input terminal of OR gate 14-30.
The output terminal of F is connected to the input terminal of OR gate 14-3F, and the output data of OR gates 14-30 to 14-3F becomes the data written to bit map memory 1. As is clear from FIG. 3 described above, if it is not the start/end, all shifter out data is written, so all the start/end gate signals from the control ROM 11 are set to logic "1". and gate 14-
Shifter out through 10 to 14-1F.
Data is or gate 14-30 or 14-3
For example, in the case of the start end, the start and end gate signals of the control ROM 11 from bit 0 corresponding to R/M/W shown in FIG. 3B to before C are logic "0". and the lead out data is at OR gate 14-30 or 14.
-Output to 3F. Similarly, in the case of termination, the start and end gate signals of the control ROM 11 are set to logic "0" for up to bit 15 after d, which corresponds to R/M/W shown in FIG. 3C. Control ROM
11 is, for example, 256×4 as shown in Figure 8.
In the case of ROM, four are used, and as shown in Fig. 1, the remainder c of the write start address with respect to the constant length N and the remainder d of the write end address with respect to the constant length N are selected by the start and end end notification signals. The signals 0 to 15 read out using the address as the starting and ending gate signals shown in FIG.

FIG. 9 is a diagram showing the occurrence pattern of the beginning and end of the write destination, and FIG. 10 is a diagram showing the occurrence pattern when the beginning and end of the write destination are within the same access unit. Figure 9A is the write start address of the access unit
The figure shows an example in which the write end address _XD is different from _XC and the access unit is 16 bits, and the shaded area shows the part where shifter out data is written. FIG. 9B shows a case where the write start address X _C and the write end address X _D of the access unit are the same, and both c and d are from 0 to 15.
Since it is actually impossible for c<d, the ninth
A pattern can only exist below the diagonal dotted line in figure b. FIG. 10 specifically shows this pattern. When the pattern shown in FIG. 10 is made to correspond to the start and end gate signals of the control ROM 11 shown in FIGS. You can configure the ROM to do this. As a result, only the bits corresponding to the shaded areas send shift out data through the AND gates 14-10 to 14-1F shown in FIG.
Since the read-out data is sent through 14-2F, read-modify write using the lead-out data is executed.

FIG. 11 is a flow chart showing the flow of processing by the control circuit. The flow of the process will be explained below with reference to FIG.

Check whether it is the start or end.

If it is the start end, process is performed; if it is neither the start nor the end, process is performed; if it is the end, process is performed.

Set the starting gate. Perform the following processing.

A comparison is made between the start end a of the read destination and the start end c of the write destination.

When a>c, the process is performed, and when a≦c, the process is performed.

Read address _XA of bit map memory. Perform the following processing.

Set X _A address + 1 as the new X _A address. Perform the following processing.

Turn off the start and end gates. Perform the following processing.

Set the termination gate. Perform the following processing.

Read address _XA of bit map memory. Perform the following processing.

Read/modify/write to bit map memory address _XC . If it is not the beginning or end, c and d are turned off as explained with reference to FIGS. 7 and 8, and the AND gates 14-20 to 2F of the multiplexer 14
is turned off, so shift-out data is written. Perform the following processing.

Check whether X _C = X _D.

If X _C = X _D , process X _C
If not =X _D , perform processing.

Set X _A address + 1 as the new X _A address. Perform the following processing.

Set X _C address + 1 as the new X _C address. Return to next process.

Check whether y _C = y _D.

If y _C = y _D , the process is terminated, and if y _C = y _D , then the following process is performed.

X Read address _A and return to the first address. Perform the following processing.

Set _yC address +1 as the new _yC address. Return to next process.

In the processing in the scanning line direction, the processing for one access unit is completed by the processing up to this point, and when the processing up to this point is repeated, the processing for one line in the scanning line direction is completed. Then, processing for the next line begins.

FIG. 12 is a diagram showing an example of application of the present invention. When moving windows to a position where they overlap on the same bit map display screen, as shown in Figure 12, a You can save the window to a spare area that is not displayed () and then move it to a specified location in the display area () again, or prepare a standard pattern (A, B, C, D) in the preliminary area and use this standard pattern. It is also possible to transfer the pattern to the display area at high speed ().

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the start and end of the window and the start and end of the movement destination are aligned by executing read, modify, and write using a shift circuit and a multiplexer. A window consisting of a free bit length can be moved at high speed without being restricted by the access unit of the bit map memory, and the speed and efficiency of data processing can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention;
Figure 2 shows an example of a window and destination specified by the coordinates of two points, Figure 3 shows an overview of data shift and read/modify/write, and Figure 4 shows a CRT display. FIG. 5 and FIG. 6 are diagrams showing a concrete configuration example of the temporary storage register and shifter section, and FIG. 7 is a diagram showing a configuration example of the multiplexer 14. Figure 8 is a diagram showing an example of the configuration of the control ROM, Figure 9 is a diagram showing the occurrence pattern of the beginning and end of the write destination, and Figure 10 is the case where the beginning and end of the write destination are within the same access unit. FIG. 11 is a flow chart showing the flow of processing by the control circuit, and FIG. 12 is a diagram showing an application example of the present invention. 1...Bit map memory, 2...Read address register, 3...Write address register, 4...
...Write end address register, 5...Comparator, 6...
...Subtractor, 7, 7-1 and 7-2...Temporary storage register, 8...Shifter, 9...Start gate, 10...
... Termination gate, 11 ... Control ROM, 12 ...
Control circuits, 13, 14 and 16...Multiplexer, 15...Bit map display, 1
7...Memory address register, 18...Display counter, 19...Shift register, a...
Remainder of read start address with respect to fixed length N, c...Remainder of write start address with respect to fixed length N, d...Remainder with respect to fixed length N of write end address, ...match signal, ...memory signal, ...shift signal ,...
Start/end gate signal, difference signal, start/end notification signal, 8-00 to 8-0F, 8-E0
to 8-EF, 8-F0 to 8-FF, 14-
10 to 14-1F and 14-20 to 14-
2F...and gate, 8-0 to 8-F and 14-30 to 14-3F...or gate.

Claims (1)

[Claims] 1 The window specified by the coordinates of two points on the bit map memory is accessed in units of a fixed bit length N in the scanning line direction, and the window specified by the coordinates of the two points is accessed. A method for controlling the movement of a window on a bit map memory in which data is moved to a rectangular portion of the window, a temporary storage means for reading out and storing data sequentially in accordance with the above unit from the read-out head address of the window, and storing the data in the temporary storage means. a shift means for shifting the data by a predetermined number of bits and outputting the data in units of bit length of the above unit, and either the data output by the shift means or the data read from the write address of the rectangular part according to the above unit. At least data selection means selects and sends it to the bit map memory as write data at the write address, and control means performs overall control, and the control means determines the remainder of the bit length N of the read start address. The number of bits to be shifted by the shifting means is determined based on the difference between the bit length N and the remainder of the bit length N of the first write address. determining the data to be selected by the data selection means so that the original data of is guaranteed;
When writing at the end, the shifting means determines the data to be selected by the selecting means based on the remainder of the write end address with respect to the bit length N so that the original data at the rear of the write address is guaranteed. 1. A window movement control method on a bit map memory, characterized in that the method is configured to control data selection means and data selection means.