JPS6357877B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to read control of magnetic disk storage devices.

Generally, a track format recorded on a medium in a soft sector type magnetic disk storage device is shown in FIG. 1, and a conventional address information abnormality detection circuit is shown in FIG. In Figure 1,
Signal a is the only signal representing the physical starting point position on the track, and is an index signal that is generated once every revolution of the medium. b indicates a track format, and the smallest block (hereinafter referred to as sector) for reading and writing information is divided into an ID section indicating an address section and a Dat-a section for storing information. Furthermore, as shown in C, the ID section consists of an ID address mark (IDAM) that indicates the beginning of the ID section and is recorded in a special pattern (missing), an address information section, and an IDCRC that indicates the check code of the ID section. Become. on the other hand,
In FIG. 2, 1 is an address register that stores address information specified by a program, etc., and 2 is a read data signal d read from the medium.
3, an address verification circuit detects the ID section and compares and verifies the ID part with the contents of the address register 1. Reference numeral 3 designates an index counter that counts the index signal d sent from the device. Generally, in magnetic disk storage devices,
When reading or writing information, first confirm the target area (i.e. ID verification),
Reads and writes information.

Access to a magnetic disk device involves first positioning the magnetic head on the track containing the data sought from the track number, then reading the ID, and reaching the target storage area by reading the ID and finding a match with the desired ID. The index counter counts the number of index signals (ie, the number of revolutions) read from the time when the desired track is reached until the target sector is detected. When the IDs match, a signal e (meaning address match) is output, and at that time, the address register 1 is set with the next desired address.

In the above device, when the index counter 3 exceeds a certain value (3 in this embodiment), an index overflow signal f is output as an error. (In other words, this indicates that the IDs have rotated three times without being able to match.) Causes of the error include reading errors and specifying an undefined address.

The operation is terminated due to the signal f as an error in reading the ID section.

In the case of such a method, there is a problem that if the index signal is not output due to a hardware failure or the like, the contents of the index counter will not reach a predetermined value, resulting in an abnormal hardware loop.

An object of the present invention is to solve the problems in the prior art as described above, and to reliably detect an error when reading an ID section on a magnetic disk or undefined address information, and to notify a host device of the problem. However, the purpose is to provide a means for reporting abnormal conditions.

The key point of the present invention is that in addition to the conventional circuit that detects abnormal operation by monitoring the index signal,
In the verification operation, the information recorded on the track
The purpose is to add a means to detect abnormal operation based on the number of times the ID part is read.

FIG. 3 shows an embodiment of the present invention. In the figure, numerals 1 to 3 refer to those shown in FIGS. 2 and 1. 4 is an ID counter circuit that counts the number of times the ID section on the track is successfully read in the address verification circuit; 5 is an OR gate that ORs the output of the index counter 3 and the output of the ID counter 4; .

In the ID verification operation, the address verification circuit 2 first reads the IDAM shown in the track format in Figure 1, then the IDCRC, and after confirming that there are no errors, reads the contents of the address register and the address information read from the disk. If they match, it is determined that the sector is the target sector, and an address match signal e is output.

In the above operation process, read IDCRC,
If it is confirmed that there is no error, it is determined that any ID section recorded on the track has been read normally, and at this point, the address verification circuit 2 outputs an ID detection signal j. The same signal is
It is connected to ID counter 4, and in the same circuit,
If the same signal generated during the ID verification operation exceeds a predetermined number of times (usually 2 to 3 times the number of sectors that originally exist on the track), it indicates some kind of media or hardware failure, or an undefined number of sectors. Assuming that the target sector could not be detected due to address information specified to the address register, etc.
ID overflow signal h is output. An address error signal g is output by ORing this signal with the output signal from the index counter.

As a result, if an index signal is not sent from the device due to a hardware failure, it is possible to detect an abnormality in the address information using the signal h and report the abnormality to the higher-level device. The signal h also makes it possible to detect an abnormality in the index signal a, which is an interface signal with the device. Note that when the address matching circuit 2 detects a target sector, an address match signal e is output, and the contents of the address register 1 are updated by this signal to indicate the next target sector address. At the same time, the index counter 3 and ID counter 4 are set to their initial values and continue to operate.

Since there are many IDs on one track, even if some of them cannot be read for some reason, errors can be detected reliably.

Therefore, according to the present invention, it is possible to reliably detect that an address match cannot be obtained, and as a result, the cause of the failure can be easily analyzed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the format of information on a track, FIG. 2 is a diagram showing a conventional address information abnormality detection circuit, and FIG. 3 is a diagram of an abnormality detection circuit according to the present invention. 1... Address register, 2... Address verification circuit, 3... Index counter, 4...
ID counter, 5...OR gate, a...index signal, d...read data signal, e...address match signal, f...index overflow signal, g...address error signal, h...
ID overflow signal, j...ID detection signal.

Claims (1)

[Claims] 1 A means for comparing the address of the sector to be accessed with the sector address read from the medium, and counting the number of index signals generated each time the medium rotates, until the count value reaches a predetermined value. an error detection device for address information in a magnetic disk storage device, which outputs an error signal when the comparison matches, and a first counter that is cleared when the comparison matches, the number of sector address signals read from the medium; count and
An abnormality detection device for address information, comprising a second counter that outputs an error signal when the count value reaches a predetermined value and is cleared when the comparison results in a match.