JPS6357984B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock synchronization circuit in a demodulation section for PSK modulated command signals of an artificial satellite.

Conventionally, a circuit as shown in FIG. 1 has been used as a demodulator for PSK modulated waves. In the figure, 10
1 is a PSK modulated wave input terminal, 102 is a demodulated data output terminal, 1 is a carrier recovery circuit, 2 is a clock synchronization circuit, 3 is a clock extraction circuit, 4 is a phase detection circuit, and 5 is an identification circuit. A part of the PSK modulated wave input to the terminal 101 is input to the Costas type or inverse modulation type carrier wave regeneration circuit 1, and the carrier wave is regenerated. The phase detection circuit 4 compares the phases of the reproduced carrier wave and the PSK modulated wave, and demodulates the PSK modulated wave. On the other hand, a clock component of a part of the PSK modulated wave is extracted by a clock extraction circuit 3 comprising a full-wave rectifier circuit, etc., and a clock signal is reproduced by a clock synchronization circuit 2. Further, the identification circuit 5 uses the reproduced clock signal to determine whether the demodulated waveform output from the phase detection circuit 4 is "1" or "0", and outputs it to the terminal 102 as demodulated data.

The PSK demodulator configured in this way requires two phase-locked circuits, one for carrier wave recovery and one for clock synchronization, which complicates the configuration of the demodulator and requires small size, light weight, and low power consumption. It is unsuitable for command demodulators mounted on artificial satellites. Furthermore, as a conventional simple command demodulator, there is a system in which the carrier frequency and the clock frequency are made the same and the command demodulator serves both carrier wave recovery and clock recovery. However, when used in deep space satellites, the data rate, or clock speed, must be extremely slow to ensure line margin, and it is impossible to make the carrier frequency and clock frequency of this system the same. Become.

In order to solve these drawbacks, the present invention uses a carrier wave set to N times the clock frequency and uses the clock extracted when a clock synchronization pattern is received to reset the N-divided counter of the recovered carrier wave and synchronize the clock. Its purpose is to provide a simple clock synchronization circuit.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the invention.
In the figure, 11 is a phase detection circuit, 12 is a voltage controlled oscillation circuit, 13 is a filter, 14 is a phase comparison circuit, 1
5 is an inverse modulation circuit, 16 is a differentiation circuit, 17 is an integration circuit, 18 is an N frequency division counter, and 19 is an identification circuit. First, the two-phase PSK modulated wave input to the terminal 101 is transmitted to the voltage controlled oscillation circuit 1 by the phase detection circuit 11.
Phase detection is performed by the output of 2. The inverse modulation circuit 15 modulates the input PSK modulated wave using this phase detection signal, and restores the phase of the input modulated wave to obtain a continuous phase carrier wave. On the other hand, in the phase comparison circuit 14, the output of the inverse modulation circuit 15 and the voltage controlled oscillation circuit 12 are
The phase of the voltage controlled oscillation circuit 12 is controlled through the filter 13. These circuits constitute a phase-locked loop for carrier wave regeneration.

Next, the reproduction of the clock signal will be described. The phase detection data output from the phase detection circuit 11 is differentiated by a differentiation circuit 16 to extract a clock component. This clock component is counted in the integrating circuit 17, and when n clock signals are counted during a certain period, for example, m clock period (m>
n) It is determined that the clock has definitely been detected, and a reset signal is sent to the N frequency division counter. On the other hand, the N frequency division counter 18 is the output of the voltage controlled oscillation circuit 12,
That is, the frequency of the reproduced carrier wave is divided by N, and the carrier frequency o in the modulated wave and the clock frequency c of the data to be modulated are in a relationship that is a multiple of o=Nc. The output of the carrier wave N frequency division counter 18 normally has N different phase states from the initial value of the counter. In other words, the clock period of the output of the N-divided counter 18 is recovered, but there are N different phase uncertainties. In order to synchronize this phase with the phase detection data output from the phase detection circuit 11, when the clock signal is reliably detected by the above-mentioned reset signal, N
Reset the frequency division counter 18. Identification circuit 19
Then, the phase detection data is determined based on the reproduced clock signal, and demodulated data of "1" or "0" is output to the terminal 102.

Next, the operation of the circuit of FIG. 2 will be further explained using the waveform diagrams of FIGS. 3a to 3f. FIG. 3 shows a case where the carrier frequency o is four times the data clock frequency c, that is, N=4, and the waveforms a to f correspond to those in FIG. 2, respectively.

The phase modulated wave a input to the input terminal 101 is
The phase of the reproduced carrier wave b is detected by the phase detector 11 and becomes reproduced data c. Also, the reproduced carrier wave b is 4
The frequency is divided by four by the frequency division counter 18 and becomes the output f. As can be seen from FIG. 3f, the output f has four different phase states.

The differentiating circuit 16 extracts the polarity change point of the reproduced data c and outputs a differential pulse d.
is disturbed by noise, etc., and is not necessarily a definite differential pulse. For this reason, the integration circuit 17 (specifically constituted by a counter)
Then, the differential pulse d is counted, and during a certain period (m
When the number of differential pulses d counted by the clock (clock) exceeds a certain threshold (n), the integrating circuit 17 outputs a reset pulse e. (FIG. 3 e shows the pulse shown in FIG. 3 d when the count value exceeds the threshold value.) This pulse e causes the four clock phases .about. to be uniquely fixed to the phase. That is, the clock corresponding to the data conversion point is reproduced.

As described above, the present invention does not require a phase synchronization circuit for reproducing clock signals, and can synchronize clock signals with a simple circuit, thereby enabling command demodulation for satellites that require small size, light weight, and low power consumption. Ideal for utensils, etc.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional PSK demodulation circuit.
FIG. 2 is a block diagram of an embodiment of the clock synchronization circuit according to the present invention, and FIGS. 3a to 3f are waveform diagrams for explaining the operation of the circuit shown in FIG. 2. In the figure: 1...Carrier recovery circuit, 2...Clock synchronization circuit, 3...Clock extraction circuit, 4...Phase detection circuit, 5...Identification circuit, 11...Phase detection circuit, 1
2... Voltage controlled oscillation circuit, 13... Filter, 1
4... Phase comparator circuit, 15... Inverse modulation circuit, 16
... Differentiation circuit, 17 ... Integration circuit, 18 ... N frequency division counter, 19 ... Discrimination circuit.

Claims (1)

[Claims] 1 In PSK modulation and demodulation, which includes a synchronization pattern for clock extraction and shifts the phase of the carrier wave using data pulses, the carrier wave frequency o and the clock frequency
A carrier wave regeneration circuit in which c is set to have a multiple of o=Nc, a counter that divides the frequency of the regenerated carrier wave by N, and a phase detection circuit that detects the phase of the input PSK modulated wave using the regenerated carrier wave. count the clock signals obtained from the output of the phase detection circuit when receiving a predetermined synchronization pattern, and reset the N frequency division counter when the clock signal is detected n times (m>n) during m clock periods. A clock synchronous circuit characterized by: