JPS635826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binary code conversion method that is applied when transmitting a binary code using a magnetic recording/reproducing device, a rotating disk, or the like as a medium.

One of the conversion methods is to convert an m-bit data word into an n-bit code word; one example is 3PM (m=3, n=6).
(Three position modulation) method is known. This means that there are at least 2
Therefore, the minimum distance between two inversions (transitions) is 3. If the period of a bit cell of a data word is T, then in the case of the 3PM system,
The minimum reversal interval Tmin and maximum reversal interval Tmax between the two reversals are (Tmin=1.5T) (Tmax=6T). The longer the minimum inversion interval Tmin, the higher the data density, which is preferable, and the shorter the maximum inversion interval Tmax, the easier it is to reproduce the clock on the receiving or reproducing side. The 3PM method has a lower Tmin than other methods.
Although it has the advantage of a large Tmax, it has the problem of a large Tmax, and is not necessarily suitable for self-clocking.

An object of the present invention is to realize a conversion method that has a data density equivalent to that of the above-mentioned 3PM method, and can also shorten the maximum inversion interval.

In the present invention, first, when the bits of the input data of the binary code change from the second value to the first value,
The bit cells of the input data are inverted at the first reference point. In the following explanation, the first value is assumed to be a high level (“1”), the second value is assumed to be a low level (“0”),
The first reference point of the bit cell is its center and its second reference point is its boundary. However, these relationships are completely equivalent even if they are replaced. The above conversion rule is the same as NRZI, so if we consider the case where there are consecutive “1”s, we will get (Tmin=T) and “0”s will be consecutive. As it becomes clear if
Tmax will be unrestricted. Therefore, in the present invention, when "1" is consecutive, the above conversion rule is modified to set (Tmin = 1.5T), and when "0" is consecutive, this conversion rule is modified, for example (Tmax = 4T).

A preferred embodiment of the present invention will be described below. Each of Figures 1 to 3 shows the conversion rules, and the time chart included in each figure shows the input data, the converted transmission waveform, and the converted data. , "1", it is assumed that an inversion occurs at the leading edge of the 0.5T bit cell. Of course, in the case of "1", inversion may occur at the trailing edge.

As shown in FIG. 1A, in the case of input data of 010, inversion occurs at the center of "1" as described above. When there are two consecutive “1”s, that is, 0110, as shown in Figure 1B, an inversion occurs at the middle of the first “1” and an inversion occurs at the boundary after the next “1”. bring about At this time, the reversal interval is 1.5T (=
Tmin). Even when 01110 and three "1"s occur in succession, as shown in FIG. 1C, an inversion occurs at the center of the first "1" and an inversion occurs at the boundary after the last "1". In this case, the reversal interval is
It becomes 2.5T. In addition, when there are four or more consecutive "1" bits, the consecutive bits are divided into two bits at the boundary of the bit cell, and if there is a remainder as a result of this division, the consecutive "1" bits are separated. The 5 bits before the first “0” bit after the
Separate the bit and the following two bits by a boundary,
Causes the inversion to occur at the rear boundary of this partition.

As shown in Figure 1D, Figure 1F, Figure 1H, and Figure 1J, it is possible to divide every 2 bits without any remainder so that 4, 6, 8, or 10 "1"s are consecutive. If possible, the inversion interval for the first 2 bits will be 1.5T, and all other 2 bits will be
In terms of bits, this is 2T. Also, as shown in Figure 1E, if there are five consecutive 1's, divide them into 3 bits and the following 2 bits according to the above rules, and set the inversion interval of the first 3 bits. 2.5T, and the inversion interval of the latter 2-bit unit becomes 2T. Furthermore, as shown in Figure 1G, Figure I, and Figure K, respectively, 7 pieces, 9 pieces, and
If there are 11 consecutive "1's", there will be a remainder when dividing in units of 2 bits, so the 5 bits before the first "0" bit are divided into 3 bits and the following 2 bits. Separate at boundaries and cause inversion at each subsequent boundary.

As above, the minimum reversal interval Tmin is set to 1.5T.
It can be done. Furthermore, the maximum reversal interval that appears when "1" continues is 3T. What should be noted here is that an inversion interval of 3T (or 2.5T) occurs for the previous 3 bits of the last (or all) 5 bits in the continuous "1" bit pattern, so the 3T The reversal interval after (or 2.5T) is always 2T. Next “0”
A conversion rule applied to a continuous pattern, that is, a rule that can limit the maximum inversion interval Tmax to 4T will be explained with reference to FIG. 01 and 001 as shown in Figure 2A and Figure 2C
If the previous two bits are 01, an inversion occurs at the center of "1", as understood from the above explanation.
In addition, as shown in Figure 2 and Figure D, 01 and 001
If the previous two bits are 11, an inversion occurs at the boundary after the "1". In FIG. 2E and subsequent figures, the transmission waveform when the two bits before the consecutive "0" are 01 is shown, and the transmission waveform when it is 11 is shown with a broken line.

If there are two or more consecutive “0”s, the bit cells are inverted at a boundary that satisfies the fact that they are at least 3T from the previous inversion, for example 3T, and are at least 1.5T away from the center of the first “1” that appears after. It is done so as to cause As shown in Figure 2E, “0” is 3
When the number 1 is consecutive, the above condition is not satisfied, so a reversal occurs at the center of "1", and the reversal interval 4T at this time becomes the maximum reversal interval Tmax.
It is only in this case that Tmax occurs. Second
As shown in Figure F, Figure G, and Figure H, if there are 4, 5, and 6 consecutive 0's, the above condition is satisfied and 3.5T (or 3T) is reached from the previous reversal. The reversal occurs at a distance of . Also, Figure 2 I
As shown in , if there are 7 consecutive “0”s,
A reversal occurs once at an interval of 3.5T (or 3T), and a reversal occurs at a position of 3T from this intermediate reversal. “0” is
In the case of 15 consecutive pieces, as shown in Figure 2 J,
Four degrees of reversal will occur during the succession.
Furthermore, as shown in FIGS. 2K and 2L, respectively,
When 16 and 17 "0"s occur consecutively, a 5 degree reversal occurs during the succession.

As explained above, no matter how many “0”s are in a row,
The maximum reversal interval Tmax will be limited to 4T. As can be seen from FIG. 2, even when "0"s occur continuously, 3T appears as an inversion interval, similar to when "1s" occur continuously. Therefore, when decoding, it seems impossible to distinguish between continuous "0" and continuous "1". but,
A 2T reversal interval never appears after the 3T reversal interval that occurs in the case of continuous “0”, and other 1.5T, 2.5T, 3T, and 3.5T reversal intervals appear,
On the other hand, as described above, a 2T reversal interval always appears after the 3T reversal interval that occurs in the case of continuous "1"s. Using this difference,
Can be decoded.

FIG. 3 shows an example of an encoder that performs code conversion as described above. In FIG. 3, 1 represents a logic circuit, 2 represents a 5-bit shift register, 3 represents a 2-bit shift register, and 4 represents an 8-bit shift register. Input data is supplied from input terminal 5, and shift register ₂ is operated by shift clock CP1 from terminal 6. The shift registers 3 and 4 are operated by a shift clock _CP2 from a terminal 7, and two bits of the output of the logic circuit 1 are loaded by a load pulse LD from a terminal 8. Shift clock _CP2 has twice the frequency of shift clock _CP1 .
Furthermore, the encoded output data appears at the serial output terminal 9 of the shift register 4, and the 7 bits A to G of this shift register 4 are output to the logic circuit 10.
supplied to The logic circuit 10 is supplied with the first bit _a1 of the shift register 2 and generates an output bit x based on the following logical formula.

x=(A+B)・(+)・(+)・₁ +(F+G)・a 1 5 bits of shift register 2 a ₁ , a _{2 ,} a ₃ , a ₄ ,
A total of 6 bits, _a5 and the output bit x of the logic circuit 10, are supplied to the logic circuit 1. Logic circuit 1 generates a 2-bit output (b ₁ b ₂ ) expressed by the following logical formula from these 6 bits. Of the 5 bits of input data taken into the shift register 2, bit _a2 is converted to two bits ( _{b1b2 )} .

As shown in FIG. 4A, one bit of input data is transferred to shift register 2 at the rising edge of shift clock _CP1.
be taken in. The contents of shift register 2 do not change until the next rising edge of shift clock _CP1 is supplied, and this period constitutes one operation cycle ECC of the encoder. The 2 bits (b ₁ b ₂ ) loaded into the shift register 3 in the previous cycle are sent to the shift register 4 by the shift clock CP ₂ shown in FIG. 4B, and become the 2 bits of FG. At this time, bit x formed in logic circuit 10 is generated based on the above-mentioned logical formula, and a 2-bit output corresponding to the above-mentioned logical formula appears from logic circuit 1.
This output b ₁ b ₂ is the load pulse LD shown in Figure 4C.
It is loaded into the shift register 3 by the rising edge of . Thereafter, this operation is repeated, and output data conforming to the above-mentioned rules can be obtained at the output terminal 9.

The encoder shown in FIG. 3 is only an example,
Various modified configurations are possible. One of them is a configuration in which a ROM is used in place of the logic circuit 1.

When transmitting the output of the encoder described above, for example when recording on a disc similar to a video disc, a frame synchronization signal FS is added. Unlike magnetic recording and reproducing machines, video discs cannot add a synchronization signal with a third value different from the binary data, so a frame synchronization signal FS must be inserted into the data stream. The frame synchronization signal FS must have an identified bit pattern even if it is inserted into the data stream. In other words, it must have a bit pattern that never appears in the data without transmission errors. An example of the code conversion method described above that satisfies this condition is shown in FIG. In other words,
The pattern is that a 4T reversal interval is followed by a 3.5T reversal interval, which is further followed by a 2T reversal interval.
As previously mentioned, a maximum reversal interval Tmax of 4T occurs only in the case shown in FIG. 2E, starting and ending at the center of the bit cell. Therefore, the later reversal at the end of 3.5T ends at the boundary, and the appearance of the reversal interval of 2T after this means that
It never occurs. Of course, this frame synchronization signal FS indicates not only frame synchronization but also bit synchronization because its inversion position has a predetermined relationship with respect to the data bit cells.

FIG. 6 shows the configuration of an example of a decoder. The decoder is supplied with playback data from the input terminal 11.
15-bit shift register 12 and logic circuit 14
and a latch circuit 15, and decoded output data can be obtained at an output terminal 17 of the latch circuit 15. Shift register 12 receives shift clock _CP3 from terminal 13.
(cycle of 0.5T), the reproduced data is taken in one bit at a time. The logic circuit 14 is a shift register.
12 bits from c ₁ to _{c 15} except c ₁₀ , c ₁₂ and c ₁₄ are supplied to generate an output y based on the following logical formula.

y=c ₆ +c ₅・₈・c ₁₁・c ₁₅ +c ₉・(c ₃・c ₁₃ +c ₄ +c ₅ )+c ₇・(c ₁・c ₁₁ +c ₂ +c ₃ +c ₄ ) The latch circuit 15 has terminals A latch pulse CP ₄ from 16 latches the output y of logic circuit 14. The period of this latch pulse _CP4 is twice (T) that of the shift clock _CP3 . Then, the boundary of the bit cell of the reproduced data is c ₂ of the shift register 12.
and between c ₃ , between c ₄ and c ₅ , between c ₆ and c ₇ , between c ₈ and c ₉ , between c ₁₀ and c ₁₁ , between c ₁₂ and c ₁₃ , c ₁₄
The latch pulse _CP4 is generated in synchronization with the timing that coincides with the timing between the timing and _c15 . In the encoder described above, it is assumed that the 2-bit output (b ₁ b _{2 )} is generated from the logic circuit 1 in correspondence with bit a ₂ of the input data. The two bits of _c6 become (b ₁ b ₂ ), and the bit taken out to the output terminal 17 at that time becomes a ₂ .

Different from the configuration shown in FIG. 8, various modifications such as using a ROM in place of the logic circuit 14 and latch circuit 15 are possible.

As understood from the description of one embodiment above,
According to the invention, the minimum reversal interval is 1.5T,
The binary code can be converted such that the maximum inversion interval is, for example, 4T. Therefore, data density equivalent to that of the 3PM method can be achieved, and the maximum inversion interval can be made shorter than 6T. When a value distinguishable from data cannot be used for a synchronization signal, such as a PCM audio disc using a video disc, it is necessary to perform synchronized playback from a data stream on the playback side. The present invention is suitable for use in such cases because it is possible to shorten the maximum reversal interval. However, in reality, the maximum inversion interval of 6T or more may be acceptable depending on the time axis fluctuation included in the reproduced data. Furthermore, the present invention has the advantage that encoders and decoders with simple configurations can be used.

[Brief explanation of the drawing]

1 and 2 are schematic diagrams used to explain the conversion rules in one embodiment of the present invention, FIG. 3 is a block diagram of an example of an encoder, and FIG. 4 is a time chart used to explain the encoder. , FIG. 5 is a diagram used to explain the frame synchronization signal, and FIG. 6 is a block diagram of an example of a decoder. 1 is a logic circuit, 2, 3, 4, and 12 are shift registers, and 10 and 14 are logic circuits.

Claims (1)

[Scope of Claims] 1. Input data of a binary code consisting of a bit string in which each bit has a first or second value is input to the first reference point of a bit cell of a predetermined bit of the input data or to this first reference point. In the binary code conversion method for converting into a transmission waveform having an inversion at a position corresponding to a second reference point located 0.5T (where T is a period of 1 bit cell of the input data) after the reference point of If a bit with the first value in the input data follows a bit with the second value, then
The above-mentioned inversion is caused in the above-mentioned transmission waveform at a position corresponding to the above-mentioned first reference point of a bit cell having a value of When the plurality of bits are two bits, the above-mentioned inversion is caused in the transmission waveform at the position corresponding to the second reference point of the bit cell of the last bit of these two bits, and when the plurality of consecutive bits are three bits,
The above-mentioned inversion is caused in the above-mentioned transmission waveform at the position corresponding to the above-mentioned second reference point of the last bit of the 3-bit bit cell, and this continuous plurality of bits
If it is more than 2 bits, the consecutive bits are
If there is a remainder as a result of this division, the last 5 bits of this continuous plurality of bits are divided into 3 bits and the following 2 bits, and each of the divided 2 bits or 3 bits is The above-mentioned inversion is caused in the above-mentioned transmission waveform at a position corresponding to the above-mentioned second reference point of the bit cell of the last bit of the bit, and when a plurality of bits having the above-mentioned second value are continuous in the above-mentioned input data, the above-mentioned transmission waveform To,
from the first reference point of the bit cell of the first bit having the first value that is 3T or more away from the preceding inversion and which follows the plurality of bits having the second value in the input data;
A binary code conversion method characterized in that the above-mentioned inversion is caused at a position corresponding to the above-mentioned second reference point that satisfies a distance of 1.5T or more. 2. The binary code conversion method according to claim 1, wherein the first and second reference points are the center and boundary of the bit cell, respectively.