JPS6358372B2 - - Google Patents
Info
- Publication number
- JPS6358372B2 JPS6358372B2 JP54073367A JP7336779A JPS6358372B2 JP S6358372 B2 JPS6358372 B2 JP S6358372B2 JP 54073367 A JP54073367 A JP 54073367A JP 7336779 A JP7336779 A JP 7336779A JP S6358372 B2 JPS6358372 B2 JP S6358372B2
- Authority
- JP
- Japan
- Prior art keywords
- cell
- cells
- input
- notch
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、半導体集積回路装置の製造方法に関
し、特に大規模集積回路装置をレイ・アウトする
際に用いられているセルの改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to improvements in cells used in the layout of large-scale integrated circuit devices.
例えば、ビルデイング・ブロツク、マスタ・ス
ライスなどの方式で集積回路装置を設計する場
合、装置はセル（単位素子集合あるいは単位回路
集合）の領域と配線の領域とに分けられている。
そして所要種類のゲートをそれぞれセルにしてフ
アミリイを構成しておき、レイ・アウトを行なう
際には、所要セルを適宜組合せて配置し、それ等
セル間の配線をするようにしている。 For example, when designing an integrated circuit device using a building block or master slice method, the device is divided into a cell (unit element set or unit circuit set) area and a wiring area.
Then, a family is constructed by using the required types of gates as cells, and when performing a layout, the required cells are appropriately combined and arranged, and wiring is made between the cells.
さて、従来、セルの構成としては、例えば第１
図にCEL1，CEL2…で指示してあるように長方形の
枠によつて画定される領域を持ち、それ等セル間
の結合は配線領域に布設した配線L1，L2…で行
なうようにするものが知られている。この型式の
ものは、セルCEL1，CEL2…間に間隙を作ることな
しに配列することが可能である。しかしながら、
配線領域が大面積になる欠点を持つている。 Now, conventionally, as a cell configuration, for example, the first
As indicated by C EL1 , C EL2 ... in the figure, it has an area demarcated by a rectangular frame, and connections between these cells are done by wiring L 1 , L 2 ... installed in the wiring area. What it does is known. This type of cell C EL1 , C EL2 . . . can be arranged without creating a gap between them. however,
The disadvantage is that the wiring area is large.
また、第２図に見られるように、同じく長方形
の枠によつて画定される領域を持ち、且つ、横方
向に入出力端子を形成したものも知られている。
この場合、隣接する二つのセルの入出力端子が例
えば電源などであつて、同ノードであれば図のセ
ルCEL2及びセルCEL3の対向縁に見られるように入
出力端子のみで結合でき、配線を必要とせず、し
かも、セル間に空隙を形成しなくても良い。とこ
ろが、隣接する二つのセルの入出力端子が異なる
ノードである場合には、例えばセルCEL1とセル
CEL2の対向縁、或いはセルCEL3とセルCEL4の対向
縁に見られるように空隙を形成しておかなければ
ならない。従つて、配線領域の面積が低減されて
も、前記空隙で相殺されてしまう場合もある。 Furthermore, as shown in FIG. 2, a device having a region similarly defined by a rectangular frame and having input/output terminals formed in the horizontal direction is also known.
In this case, if the input/output terminals of two adjacent cells are, for example, a power supply, and are on the same node, they can be connected only through the input/output terminals, as seen on the opposite edges of cells C EL2 and C EL3 in the figure. No wiring is required, and there is no need to form gaps between cells. However, if the input/output terminals of two adjacent cells are different nodes, for example, cell C EL1 and cell
A gap must be formed as seen at the opposing edges of C EL2 or the opposing edges of cell C EL3 and cell C EL4 . Therefore, even if the area of the wiring region is reduced, it may be offset by the void.
本発明は、各セルを常に密接して配置すること
ができるように、しかも、配線領域を節減できる
ようにしてチツプ・サイズの小型化、性能及び製
造歩留りの向上、コスト低減に寄与し得るように
するものであり、以下これを詳細に説明する。 The present invention enables each cell to be placed closely together at all times and also saves wiring area, contributing to miniaturization of chip size, improvement of performance and manufacturing yield, and reduction of cost. This will be explained in detail below.
本発明が基本とするところは極めて簡単であ
る。即ち、第３図に見られるように、セルCELに
於ける他のセルとの対向縁（境界部）に切欠部
CTを形成し、その切欠部CT内に入力或いは出力
の端子TMを形成したことである。 The basis of the present invention is extremely simple. In other words, as shown in Fig. 3, a notch is formed at the opposite edge (boundary) of cell CEL with other cells.
CT is formed, and an input or output terminal T M is formed within the notch CT .
このようなセルCELに於いて入出力端子TMのノ
ードの関係が第２図と同様であるとした場合の配
列は第４図に見られる通りである。即ち、セル
CEL12とセルCEL13とは切欠部CT内で配線L4にて結
合されているが、セルCEL11とセルCEL12、或いは、
セルCEL13とセルCEL14は切欠部CT内での結合はさ
れていない。そして、各セルCEL12，CEL13…は互
に密接して配列されている。尚、配線領域が小面
積で済んでいることは明らかである。 In such a cell CEL , the arrangement is as shown in FIG. 4, assuming that the relationship between the nodes of the input/output terminals T M is the same as that in FIG. 2. That is, the cell
C EL12 and cell C EL13 are connected by wiring L 4 in the notch CT , but cell C EL11 and cell C EL12 or
Cell C EL13 and cell C EL14 are not connected within the cutout CT . The cells C EL12 , C EL13 . . . are arranged closely to each other. Note that it is clear that the wiring area only needs to be small.
第５図は本発明を説明する為のより具体的なセ
ル及びその配列を表わす説明図であり、既出の記
号と同記号で指示した部分は同部分である。 FIG. 5 is an explanatory diagram showing a more specific cell and its arrangement for explaining the present invention, and parts indicated by the same symbols as those already mentioned are the same parts.
図に於いて、CEL21は２入力NORゲートセル、
CEL22は２入力NANDゲートのセル、CEL23は３入
力NANDゲートのセル、VDDは正電位の電源ライ
ン、VSSは接地電位の電源ライン、GAはゲート電
極・配線、OTは出力端子、Rchはｐチヤネル・ト
ランジスタ部分、Nchはｎチヤネル・トランジス
タ部分をそれぞれ示している。 In the figure, C EL21 is a 2-input NOR gate cell,
C EL22 is a 2-input NAND gate cell, C EL23 is a 3-input NAND gate cell, V DD is a positive potential power line, V SS is a ground potential power line, G A is the gate electrode/wiring, O T is the output In the terminals, R ch indicates a p-channel transistor portion, and N ch indicates an n-channel transistor portion.
本例では、１点鎖線がセル枠を、破線がアルミ
ニウム配線をそれぞれ示している。また、各セル
CEL21…を密接配列すると電源ラインVDD或いは
VSSは自動的に結合されるが、これは各セルCEL21
…とも同一電位であるから問題はなく、かえつて
好都合である。図から判るように、セルCEL22即
ち２入力NANDゲートの出力端子OTが配線L4を
介してセルCEL23即ち３入力NANDゲートの一つ
の入力端子に結合されている。 In this example, the one-dot chain line indicates the cell frame, and the broken line indicates the aluminum wiring. Also, each cell
If C EL21 ... are closely arranged, the power line V DD or
V SS is automatically combined, but this means that each cell C EL21
Since both have the same potential, there is no problem, and on the contrary, it is convenient. As can be seen, the output terminal O T of the cell C EL22 , ie, the 2-input NAND gate, is coupled to one input terminal of the cell C EL23 , ie, the 3-input NAND gate, via the line L 4 .
前記説明したいずれの実施例に於いても切欠部
CTはセルとセルとの対向縁に、於ける略中央に
形成されているが、これは前記実施例に限定され
るものではなく、例えば対向縁の上隅角（或いは
下隅角）などでも良く、第６図はそれを例示する
ものである。 In any of the embodiments described above, the notch
C T is formed approximately at the center of the opposing edges of the cells, but this is not limited to the above embodiment; for example, it may be formed at the upper corner (or lower corner) of the opposing edges. Well, FIG. 6 illustrates this.
第６図に見られるセルFF1，FF2はフリツプ・
フロツプ回路であり、セル内配線Lio11及びLio12は
共通信号の信号線S3で配線領域を使用することな
く結線され、また、セル内配線Lio21及びLio22は
別々の信号線S1，S2で結線されるが、セルの切欠
部CTの存在に依りセルFF1，FF2を密接させても
支障は生じない。 Cells FF 1 and FF 2 seen in Figure 6 are flip-flops.
It is a flop circuit, and the intra-cell wiring L io11 and L io12 are connected by a common signal signal line S 3 without using a wiring area, and the intra-cell wiring L io21 and L io22 are connected by separate signal lines S 1 , Although the cells FF 1 and FF 2 are connected in close contact with each other due to the existence of the cell notch CT , no problem occurs.
以上の説明で判るように、本発明に依れば、隣
接セルと対向する縁に於ける入出力端子形成部分
に切欠部が形成され、その内部に入出力端子を設
けたセルが得られ、そのセルの複数個を配列する
場合、それ等セルの相対向する入出力端子が異な
るノードであつても密接させることができ、そし
て、それ等入出力端子の中で結合して良いものは
配線領域を使用することなく、前記切欠部内にて
結線できる。従つて、全体として占有面積は少な
くなるのでチツプ・サイズは小型化される。 As can be seen from the above description, according to the present invention, a cell is obtained in which a notch is formed in the input/output terminal forming portion at the edge facing the adjacent cell, and the input/output terminal is provided inside the notch, When arranging multiple cells, they can be placed close together even if their opposing input/output terminals are on different nodes, and those that can be connected among the input/output terminals are wired. Wires can be connected within the notch without using any area. Therefore, the overall area occupied is reduced and the chip size is reduced.
第１図及び第２図は従来例の説明図、第３図及
び第４図は本発明実施例の説明図、第５図はより
具体的に表わした実施例の説明図、第６図は他の
実施例の説明図である。
図に於いて、CEL11，CEL12…はセル、CTは切欠
部、TMは端子、L1，L2…は配線である。
1 and 2 are explanatory diagrams of a conventional example, FIGS. 3 and 4 are explanatory diagrams of an embodiment of the present invention, FIG. 5 is an explanatory diagram of a more concrete embodiment, and FIG. 6 is an explanatory diagram of an embodiment of the present invention. It is an explanatory view of another example. In the figure, C EL11 , C EL12 . . . are cells, CT is a notch, TM is a terminal, and L 1 , L 2 . . . are wirings.
Claims (1)
して定義し、複数の該セルを組み合わせて所望の
回路を構成する半導体集積回路の製造方法に於い
て、 各前記セルの枠を、隣接するセルとの対向縁に
素子が形成されない切欠部を備えた形状とし、 且つ前記単位回路の入／出力端子を該切欠部内
の枠上に設け、 複数の前記セルを密接して配置し、前記切欠部
によつて形成された対向するセル間の間隙に前記
入／出力端子同士を接続する配線を配置すること
を特徴とする半導体集積回路の製造方法。[Scope of Claims] 1. In a method for manufacturing a semiconductor integrated circuit in which a plurality of types of unit circuits are each defined as rectangular cells and a plurality of the cells are combined to form a desired circuit, , a shape including a notch in which no element is formed on an edge facing an adjacent cell, and input/output terminals of the unit circuit are provided on a frame within the notch, and a plurality of the cells are arranged closely together. . A method of manufacturing a semiconductor integrated circuit, characterized in that wiring connecting the input/output terminals is arranged in a gap between opposing cells formed by the notch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7336779A JPS55165668A (en) | 1979-06-11 | 1979-06-11 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7336779A JPS55165668A (en) | 1979-06-11 | 1979-06-11 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55165668A JPS55165668A (en) | 1980-12-24 |
| JPS6358372B2 true JPS6358372B2 (en) | 1988-11-15 |
Family
ID=13516129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7336779A Granted JPS55165668A (en) | 1979-06-11 | 1979-06-11 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55165668A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01137483A (en) * | 1987-11-24 | 1989-05-30 | Nec Corp | Magnetic head assembly |
| JPH0214480A (en) * | 1988-03-23 | 1990-01-18 | Digital Equip Corp <Dec> | Thin type head load beam slider arm for disc drive |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS594151A (en) * | 1982-06-30 | 1984-01-10 | Fujitsu Ltd | Semiconductor circuit with building block structure |
| DE102007001196B4 (en) * | 2007-01-05 | 2012-01-05 | Infineon Technologies Ag | A method of designing the layout of an integrated circuit and associated integrated circuit |
| DE102007063765B3 (en) * | 2007-01-05 | 2013-02-07 | Infineon Technologies Ag | Integrated circuit's layout designing method, involves providing cells, where maximum expansions of cells are equal in direction, and placing cells for providing layout of integrated circuit, where external boundary line has form of polygon |
-
1979
- 1979-06-11 JP JP7336779A patent/JPS55165668A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01137483A (en) * | 1987-11-24 | 1989-05-30 | Nec Corp | Magnetic head assembly |
| JPH0214480A (en) * | 1988-03-23 | 1990-01-18 | Digital Equip Corp <Dec> | Thin type head load beam slider arm for disc drive |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55165668A (en) | 1980-12-24 |
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