JPS6358524A - Portable medium - Google Patents

Abstract

PURPOSE:To perform the control actions with small power consumption without increasing the number of keys by using a control means which controls the use of a low frequency clock for the action of a control element as well as a high frequency clock. CONSTITUTION:When a key input interruption signal is supplied from a CPU incorporating a portable medium like an IC card, etc., via an OR circuit 61, the FF 62-64 of a clock control circuit 26 incorporated to the IC card are reset with an FF 56 set respectively. Then a high frequency clock oscillation circuit 67 is set under an enable state. At the same time, a NAND gate 86 is opened via an FF 63, an inverter 82, an FF 81, an FF 83, etc., and a low frequency timepiece clock is supplied to the CPU. Then the clock supplied to the CPU is switched to a high frequency clock by the clock selection signal delivered from the CPU after a period of time during which the circuit 67 has a stable action. In the same way, said clock is changed into a timepiece clock in a stand-by state after the processing is finished by the CPU. Thus the clocks are switched via the CPU without operating keys in response to each state. Then it is possible to perform the control actions with small power consumption and with no increase of the number of keys.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention has a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card for calculators, timepieces, etc., or as a terminal device. Multifunctional IC that can be used by inserting
Regarding portable media such as cards.

(Prior Art) Conventionally, IC cards have been developed and put into practical use as memory cards for writing data. In this IC card, the driving clock of the central processing unit (CPU) is driven by one type of oscillator. Some of these cards constantly oscillate the CPU clock, but most of them stop the oscillation circuit in consideration of the current consumption of the internal battery.

In addition, when restarting an oscillation circuit that has stopped for a while, a special power on switch or equivalent key is provided on the card's keyboard. .

However, the above-mentioned device has the disadvantage that the number of keys increases. Furthermore, current consumption has not been completely reduced.

(Problem to be solved by the invention) As mentioned above, this is not a completely consumption-saving operation, but it eliminates the drawback that a special key is required to cover the rise speed of the oscillation circuit. To provide a portable medium which can be operated with complete consumption saving by stopping an oscillation circuit during waiting time during operation without providing a key.

[Structure of the Invention] (Means for Solving the Problems) The portable medium of the present invention has a control element and is operated by an internally provided N source, and constantly generates a low-frequency clock. a first clock generation means for generating a high-frequency clock; a second clock generation means for generating a high-frequency clock; and when the control element is activated, the low-frequency clock from the first clock generation means is used to control the operation of the control element. At the same time, the second clock generating means starts generating a clock, and after a predetermined time has elapsed, the control means operates the control element using the stable high frequency clock generated from the second clock generating means. It consists of:

(Operation) When the control element is released from a stopped state and restarts operation, the second clock generation means starts oscillating a high-frequency clock, and the first clock continues to oscillate until the clock is stabilized by this oscillation. The control element is operated by the low frequency clock for the clock by the clock generation means, and when the clock of the second clock generation means is stabilized, the clock is switched, the processing is linked, and when the key input is held again, etc.
Immediate shooting is stopped and the second clock generating means is brought into a stopped state.

(Example of Practical Theory) Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In FIG. 2, 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, an online function that is used using a terminal described below, an offline function that allows the IC card 10 to operate independently,
and has a state in which only the clock is counted.

The above offline functions include a calculator mode that can be used as a calculator, a time display mode that displays the time according to the clock used by the user, an electronic notebook mode that allows you to register and read out addresses, names, phone numbers, etc. t
The mode includes a shopping mode in which the C card 10 is used as a credit card.

On the surface of the IC card 1o, there is a keyboard section 12 consisting of contact sections 11.2° keys arranged at positions according to the card specifications, and a display formed of a liquid crystal display element arranged on the top surface of this keyboard section 12. 13 and a magnetism generating member 14 are provided.

The contact portion 11 includes, for example, a plurality of terminals 11a to 11a.
11h. The terminal 11a is the operating voltage 8! For voltage (+5V, Vcc), terminal 11b is for grounding, terminal 11C is for output signal, terminal 11d is for reset signal, and terminals 116 to 11h are for data input/output.

The keyboard section 12 includes mode keys (Ml, M2, M3, M4) 12a for specifying processing modes, and a numeric keypad 12b.
1 and 4 arithmetic operation keys (function keys) 12C.

The mode key 12a controls operations for calculator mode (Ml), time display mode (M2), electronic passbook mode (M3), or shopping mode (~14) when offline, that is, when processing is performed only with the IC card 10. You get to choose.

The display section 13 is a 16-digit dot matrix with each digit being 5x7.

The magnetism generating member 14 is attached to an IC card in accordance with the trunk position of a magnetic card reader (magnetic head) on the reading side (not shown).
It is embedded inside the card 10.

FIG. 3 shows an IC card reading/writing unit 1 used in a terminal device such as a personal computer that handles an IC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory. - The IC card reading unit 16 is connected to the main body of a personal computer (not shown) via a cable.

Further, the electric circuit of the IC card 1o is constructed as shown in FIG. That is, the contact portion 1
1. Communication control circuit 21, reset control circuit 22, power supply control circuit 23, for example, 3 volt internal battery (1! source) 25, battery check to check whether the voltage value of this internal battery 25 is higher than the specified value. A circuit 24, a clock control circuit 26. An oscillator 27 that outputs a signal with an oscillation frequency of 1MH2, a control CPU (central processing unit) 28, a program ROM 29 in which the υItil program is recorded, a program working memory 30, and a password. A data memory 31 consisting of a PROM in which numbers (for example, 4 digits) and data are recorded, and a timer 32 used for timing during processing operations.
, calendar circuit 33, always, 32.768KH2 (7)
An oscillator (first clock generation circuit) 34 that outputs an RmJIH (low frequency) signal, a display control circuit 35, a display driver 36 that drives the display 13, and a key input circuit for the keyboard 12. 3, and a magnetism generating member control circuit 40 that controls the magnetism generating member 14.

The communication control circuit 21, the CPU 28, the ROM 29, the program working memory 30, the data memory 31, the timer 32, the calendar circuit 33, the display control circuit 35, the keyboard interface 38, and a magnetism generating member that controls the magnetism generating member 14. The control circuit 40 is connected via the data bus 20.

The communication control circuit 21 controls the terminal 16 at the time of reception.
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
0, and when transmitting, that is, parallel data supplied from one data path 2o.

The signal is converted into a serial input/output signal and output to the terminal 116 via the contact section 11. In this case, the format contents of the conversion are determined by the terminal F316 and the IC card 10.

When the reset control circuit 22 goes online, it generates a reset signal and starts the CPU 28.

When the N source control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power source after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it switches from being driven by the external power source to driving by the external power source. This is to switch to driving by the internal battery 25.

The clock control circuit 26 is an oscillation circuit (second clock) that outputs a signal at a 1MH2 excavation frequency (high frequency), which will be described later, during standby, that is, when waiting for a key input, in an offline mode in which the card operates with the internal battery 25. The generation circuit 67 is stopped, and the clock supply to the CPU 28 is also stopped, and the CPU 28 waits in a completely stopped state.

Furthermore, when the oscillation circuit 67 is restarted from a stopped state, the clock control circuit 26 controls the clock control circuit 26 for 50 seconds until stable oscillation is performed.
Between 0 and 600m5ec, the clock is set to CPU28.
It is designed to be outputted as a clock for the first person to process the first person's oyster.

Furthermore, when the clock control circuit 26 goes online, that is, when a reset signal is supplied, it outputs the watch clock as a clock for the CPU 28 for 500 to 600 m5ec until stable oscillation occurs, and then It is designed to output a 1MH2 clock.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and a transaction clock that sets, for example, world standard time when the card is issued and cannot be changed thereafter. ing.

The display unit control circuit 35 converts the display data supplied from the CPU 28 into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPU 28 into a character pattern on the display unit 13 using a display unit driver 36. It is to be displayed.

The keyboard interface 38 converts the keys input on the keyboard section 12 into key input signals and outputs the signals to the CPU 28.

When the shopping mode is specified, the magnetism generating member control circuit 40 operates according to the data supplied via the data bus 20 and the drive rate corresponding to whether the reading device is manual reading or automatic reading. By driving and controlling the magnetism generating member 14 to output magnetic information, the same state as that of a conventional magnetic stripe is created.

The power supply control circuit 23 will be explained in detail using FIG. 5. That is, inverter circuit 51.54.55
, a counter 52, a D-type flip-flop circuit (FF circuit) 53, and a semiconductor switch 56 composed of a MOSFET.
．． 58, a diode 57, and an internal battery 25.

The count value of the counter 52 is a value that is not affected by chattering from the external NWA. Diode 5 above
7 is for protecting the power supply voltage Vout, and when the power supply voltage Vcc from the outside decreases, the power supply voltage ilI! is used before the semiconductor switch 56 is turned on. The internal battery 25 protects the ma voltage (ma) out from decreasing even if the voltage Vcc decreases below the memory drive voltage.

The operation of this configuration will be described with reference to the timing chart shown in FIG. That is, when the IC card 10 is not connected to the terminal t116 through the contact section 11, the semiconductor switch 56 is on, so that the power supply voltage of the internal battery 25 is applied to the output VOUT of the power supply control circuit 22 via the semiconductor switch 56. is applied to each part as follows.

Further, when the IC card 10 is connected to the terminal 116 through the contact section 11, the external ms voltage VCC is supplied to the gate of the semiconductor switch 58, and
A clock signal CLK is supplied to a clock terminal ck of a counter 52 via an inverter circuit 51. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 53 is set by the output from the output terminal Qn. Set output Q of this FF circuit 53
As a result, a "0" signal is supplied to the gate of the semiconductor switch 58, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned off.

Therefore, electricity from outside! Voltage Vcc is applied to each part via semiconductor switch 58 as output vout of power supply control circuit 22.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the external source voltage VCC drops by 3Mt. As a result, the reset signal causes 1. The counter 52 and FF circuit 53 are reset. Then, the "1" signal is supplied to the gate of the semiconductor switch 58, the "O" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on.
The voltage m of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

The clock control circuit 26 will be explained in detail using FIG. 1. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal Ck of the FF circuit 62. The set output of this FF circuit 62 is
The machine cycle signal M1 from the CPU 28 is supplied to the clock input terminal ck of this FF circuit 63. The FF circuits 62 and 63 are used for stop mode timing. Above FF circuit 6
The set output of 3 is supplied to the data input terminal of the FF circuit 64, and the clock input terminal ck of this FF circuit 64 is supplied with the clock of 32.763KH2 from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to the data input end of the FF circuit 65, and the clock input lck of the FF circuit 65 is supplied with the 32.763 KH2 clock from the calendar circuit 33. The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output end and the other end of the NAND circuit 66.

Further, the key input interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are supplied to the reset input terminals R of the FF circuits 62, 63, and 64 via the OR circuit 61, and circuit 6
It is supplied to the set input terminal S of No. 5.

The oscillation circuit 67 includes an oscillator 27 having an oscillation frequency of the IMH2, a resistor 68, and capacitors 70 and 71.

The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 via the inverter circuit 72, and also to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

Further, the reset signal from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 76, and the clock input terminal Ck of this FF circuit 76 is supplied to an OR circuit 84, which will be described later.
output is supplied.

Further, a clock selection signal from the CPU 28 is supplied to the data input terminal D1 and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is FF
It is supplied to the data input end of the circuit 77, and this FF circuit 7
A clock input terminal ck of 7 is supplied with a clock of 32°763KH2 from the calendar circuit 33.

The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79, and the clock of 32.763KH2 from the calendar circuit 33 is supplied to the other end of the NAND circuit 79 via an inverter circuit 78. . The outputs of the seven NAND circuits are supplied to one end of a NAND circuit 80.

Further, the reset output of the FF circuit 77 is supplied to the data input end of the FF circuit 74, and the set output of this FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is used for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to the NAND circuit 80, and the outputs of the NAND circuit 80 are fed to the FF circuits 81 and 81.
3 is supplied to the clock input terminal ck of the FF circuit 81.
The set output of the FF circuit 63 is supplied to the data input terminal of the FF circuit 63 via an inverter circuit 82.

The set output of the FF circuit 81 and the FF1 path 8
The reset output No. 3 is outputted to the clock input terminal ck of the FF circuit 76 via the OR circuit 84.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is output to the CPtJ 28 as a clock signal.

The operation in such a configuration will be explained. First, the stopped state will be explained. That is, '1' is supplied from the CPtJ28 as the clock selection signal. As a result, the FF circuit ARO 77 is set. As a result, the watch clock (32,768KH2) is sent to the FF via the inverter circuit 78 and the NAND circuit 79.80.
It is led to a circuit 8L 82 and an inverter circuit 85.

Next, restarting from a stopped state will be explained.

That is, a key interrupt signal is supplied from the CPtj28. Then, the FF circuits 62, 63 and 64 are reset, and the FF circuit 65 is set.

The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 resumes oscillation.

Furthermore, by resetting the FF circuit 63, the FF circuit 8
1" is supplied to the data input end of 1. As a result, the output of the NAND circuit 80 causes the FF circuit 81 to
．． 83 is set and the gate of the NAND circuit 86 is opened. Therefore, the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

At this time, the oscillation circuit 67 normally oscillates for 50 seconds until it stably oscillates.
0 to 600m5ec is required.

As a result, the CPU 28 supplies "0" as a clock selection signal to the data input end of the FF circuit 76 500 to 600 m5eC after outputting the signal including the key input t1. is reset, and the reset output of the FF circuit 77, that is, the “1” signal is
It is supplied to the data input end of the F circuit 74.

Also, at this time, the clock (IMH2
) is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75.

As a result, the clock (1MH2) generated by the oscillation circuit 67 is transmitted to the inverter circuits 72, 73, NAND circuits 75, 80, .
The signal is sequentially output to the CPU 28 via an inverter circuit 85 and a NAND circuit 86.

As a result, by setting the clock selection signal to "O", synchronization is achieved in the FF circuit 74, and the clock clock is switched to the high-speed processing clock.

Next, a case will be described in which the processing is ended and the system is placed in a stopped state (standby state). That is, by setting the clock selection signal to "1", the FF circuits 76 and 77 are set, the set output of the FF circuit 77, that is, the "1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is opened. .Therefore, the clock for the watch consists of an inverter circuit 78, a NAND circuit 79, 80, an inverter circuit 85,
and is sequentially output to the CPU 28 via the NAND circuit 86.

As a result, the watch clock is output to the CPU 28 again.

Next, a stop signal is supplied from the CPU 28 to the data input end of the FF circuit 62. Then, the FF circuit 62 is set, and this set output is the data input 10 of the FF circuit 63.
supplied to Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and an "O" signal is supplied to the data input terminal of the FF circuit 81. As a result, the set output of the FF circuit 63 is changed to the set output of the FF circuit 81.8.
After sending two pulses at step 3, the gate of the NAND circuit 86 is closed to stop outputting the clock to the CPLI 28. As a result, the CPU 28 is brought to a halted state.

Further, the set output of the FF circuit 63 is the FF circuit 64.
After sending two pulses at step 65, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, after stopping the output of the clock to the CPtJ 28, the oscillation circuit 67 is stopped.

In this way, the clock control circuit 26 operates as an oscillator 27.
In order to cover the rising edge of crystal oscillation caused by this, the clock for the watch and the clock for the 1MH2 are effectively switched.

The calendar circuit 33 will be explained in detail using FIG. 7. That is, the oscillator 34 of 32.768 KH2
A frequency dividing circuit 91 outputs signals every second from output terminals a and b by dividing the oscillation output of the frequency dividing circuit 9.
A counter 92 that outputs a signal every 10 seconds by counting the signal from the output terminal a of 1;
A counter 93 that outputs a signal every 60 seconds, that is, every minute, by counting the signals from this counter 93, a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93, and a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93. A counter 95 that outputs a signal every 60 minutes, that is, every hour, by counting the signals from this counter 95, and a counter 96 that outputs a signal every 24 hours, that is, every day, by counting the signals from this counter 95. A counter 97 outputs a signal every 10 seconds by counting the signal from the output 1b of the circuit 91, and a signal is output every 60 seconds, that is, every minute by counting the signal from this counter 97. A counter 98 outputs a signal every 10 minutes by counting the signal from this counter 98.A counter 99 outputs a signal every 60 minutes, that is, every hour by counting the signal from this counter 99. It consists of a counter 100 and a counter 101 which outputs a signal every 24 hours, that is, every day by counting the signal from this counter 1o○.

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 1 constitute a clock for counting seconds, minutes, and hours.
01 constitutes a display clock that counts seconds, minutes, and hours. For the year, month, day, and day of the week, an interrupt request is output to the CPLI 28 based on a signal from the counter 96.101 every 24 hours. Thereby, the CPtJ 28 uses the data memory 31 to update the year, month, day and day of the week of the corresponding area. Furthermore, as shown in FIG. 8, the two clocks have a one-second reference clock phase shifted from each other, so that interrupts do not occur at the same time.

The magnetism generating member control circuit 40 will be explained in detail using FIG. 9. That is, command data supplied from the CPU 28 via the data bus 20 is supplied to the command FF circuit 110. This FF circuit 11
0 consists of four FF circuits, and depending on the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track is sent from the output end 110a, a start signal is sent from the output end 110b, or a start signal is sent from the output end 110C. A clock selection signal corresponding to the drive rate for the second track is output from the output terminal 110d, and a start signal is output from the output terminal 110d.

The clock input terminal cp of the FF circuit 110 has the above C
A command write start signal from the PU 28 is supplied. The clock selection signal corresponding to the drive rate indicates whether the terminal type is manual reading or automatic reading.

The clock selection signal output from the output terminal 110a of the FF circuit 110 is supplied to the input terminal S of the selection circuit 111. A signal with a frequency of 8KH2 is supplied from an oscillator (not shown) to the input terminal A of this selection circuit 111, and the input terminal B
A signal with a frequency of 4KH2 is supplied from an oscillator (not shown).

In response to the clock selection signal from the FF circuit 110, the selection circuit 111 selects the signal at the input terminal A and outputs it from the output terminal Y when the terminal type is a manual reading type.
If the type of terminal 4 is automatic reading, the signal at input terminal B is selected and output from output nAY.

The start signal output from the output ON 110 b of the FF circuit 110 and the output of the selection circuit 111 are supplied to a timing circuit 112 .

This timing circuit 112 generates a heptad clock,
Clock input terminal C of parallel/serial conversion circuit 115
The first clock d1 is supplied to the load input terminal of the parallel/serial conversion circuit 115 as a load signal. Further, the timing circuit 112 has data “0”.
circuit 116 for selecting the clock for data “1” and the clock for data “1”
is supplied to.

Further, magnetic data supplied from the CPU 28 via the data bus 20 is supplied to a data latch circuit 113, and a data write start signal is supplied from the CPIJ 28 to this data latch circuit 113. The data latch circuit 113 latches 7 bits of magnetic data supplied from the data bus 20 when a data write start signal is supplied from the CPU 28.

The data latched in the data latch circuit 113 is 7
It is supplied to the data input terminal IN of the parallel/serial conversion circuit 115 for bits. The parallel/serial conversion circuit 115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (
The output signal is converted into a 1" signal or a 0 signal) and output.

The output of the parallel/serial conversion circuit 115 is supplied to the input terminal S of the selection circuit 116. This selection circuit 11
6 selects and outputs the data "1" clock supplied from the timing circuit 112 when a 1" signal is supplied to the input terminal S, and when an "O" signal is supplied to the input terminal S. , the clock for data "0" supplied from the timing circuit 112 is selected and output.The output of the selection circuit 116 is output to the J-KFF circuit 117.
and the set output of this J-KFF circuit 117,
The reset output is adapted to be supplied to driver 118.

This driver 118 generates a magnetic field by driving the magnetism generating member 41a in response to a signal from the FF circuit 117. For example, when the FF circuit 117 is set, it generates a magnetic field as shown by arrow C, and when it is reset, it generates a magnetic field as shown by arrow d.

Incidentally, a timing chart of the main parts of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG.
For data “1” and 0, the clock cycle is
The ratio is 1:2. J-KFF with this clock
By operating the circuit 117 in the inversion mode, "1" and "0" signals in the format required as magnetic data are obtained, and the magnetism generating member 41a is driven.

Further, the data write start signal from the CPtJ28 is inverted and supplied to the set input terminal of the FF circuit 114 for empty detection, and the first clock from the timing circuit 112 is input to the reset input terminal of this FF circuit 114. It is supplied inverted. This results in
When the data of the data latch circuit 113 is loaded into the data latch circuit 115, the FF circuit 114 is set, and the set output of the FF circuit 114, that is, the buffer empty signal is supplied to the CPU 28.

As a result, the CPU 28 determines that the next data can be set, and transfers the next data to the data latch circuit 1.
Output to 13. In this way, the CPtJ28 sets data in order while sensing the output of the empty detection FF circuit 114, and after outputting all the data, turns off the command write start signal and data write start signal. There is. As a result, the timing circuit 11
2 stops generating the signal, and the operation ends.

The circuits 111 to 118 are for the first track, and the circuits for the second track also include a selection circuit 119, a timing circuit 120, a data latch circuit 121, an empty detection FF circuit 122, Parallel/serial conversion circuit 123, selection circuit 124, J-KFF circuit 12
5, and a driver 126. However, the location where the timing circuit 120 operates in quinary is different.

As described above, the magnetism generating member control circuit 40
By generating a magnetic field in accordance with the magnetic data of a predetermined credit card supplied from the PU 28, the same signal as when reading a conventional magnetic stripe is supplied to a magnetic head (not shown) on the reader side. It has become so.

Next, the operation in such a configuration will be explained.

First, we will explain the offline function used by the card alone. That is, when the calculator mode is designated using the mode key 128, that is, the M1 key, the calculator can be used as a calculator using the numeric keypad 12b and the four arithmetic operation keys 12c.

Further, when the time display mode is specified using the mode key 12a, that is, the M2 key, the CPU 28 reads out the seconds, minutes, and hours for the display clock from the counters 97 to 101 in the calendar circuit 33, and displays them from the data memory 31. The year, month, day, and day of the week for the business clock are read out, converted into a specified format, and output to the display section burial circuit 35. Thereby, the display unit control circuit 35 uses an internal character generator (not shown) to convert it into a character pattern, and displays it on the display unit 13 using the display unit driver 36.

Furthermore, when the electronic width mode is specified using the mode key 12a, that is, the M3 key, the CPLJ28
Read out the address, name, phone number, etc. stored in 1.
It is displayed on the display section 13. Further, when the above-mentioned address, name, etc. are recorded in the electronic space, the user uses, for example, the numeric keypad 121). That is, rAJ is "1.1", rB
J is N, 2J, rcJ is "1.3", rDJ is "2.1"
”, ... can be specified.

When the shopping mode is designated using the mode key 12a, that is, the M4 key, the user then selects the type of contracted credit card and the type of output terminal, i.e., whether reading is assisted or automatic. Then, the CPIJ 28 reads out data (72 characters) corresponding to the selected credit from the data memory 31 and sends the data to the magnetic generation member control circuit 4.
Output to 0. Further, the CPU 28 outputs a drive rate corresponding to the selection of manual type or automatic type to the magnetism generating member control circuit 40. In general, the CPU 2B outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40.

As a result, the magnetism generating member control circuit 40 causes the magnetic head (not shown) on the reading device side to read a conventional magnetic stripe by generating a magnetic field from the magnetism generating member 41a according to the magnetic data of the credit. The same signal is provided as in the case.

As a result, in shopping mode, it can be used as a conventional credit card.

Next, the online function used by inserting the IC card 10 into the terminal v116 will be explained. That is, the IC card 10 is inserted into the insertion slot 17 of the terminal 16. Then, the IC card 10 is accepted, and the connection section inside the terminal 116 and the contact section 11 of the IC card 10 are connected. As a result, NI! from the outside via the contact portion 11! When voltage is supplied, NgAI11al11
As described above, the circuit 23 switches from being driven by the built-in battery 25 to being driven by an external N source voltage. Further, the reset control circuit 22 generates a reset signal, and the CPU 2
8. After this startup, if CPtJ2B confirms that it is running online, the program RO
Online processing is performed according to the contents of M29. This online processing involves the terminal 116 and the IC card 10.
By updating data with the IC card 10, data can be exchanged and new data can be written into the IC card 10.

As mentioned above, in order to reduce the card's current consumption, the internal oscillation circuit is used in on/off operation.
Furthermore, the waiting time due to the rise time of the oscillation circuit and the oversight of key input data can be prevented, and reliability is A.
This can extend the life of the card.

In the above embodiment, the clock is switched from low frequency to high frequency after a predetermined period of time has elapsed since the activation of CPtJ. It is also possible to switch from low frequency to high frequency mode only when it is determined that there is.

In addition, although a tC card is used, the card is not limited to this, as long as it has a data memory and a control element, and selectively performs input/output from the outside. It may be a shape.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a portable medium that can be operated with complete consumption savings by stopping the 8m circuit during operation waiting time without providing a special key.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a diagram showing the configuration of a clock control circuit, and FIG. 2 is a diagram showing the configuration of an IC.
FIG. 3 is a plan view showing the configuration of the card, FIG. 3 is a diagram showing a terminal that handles IC cards, FIG. 4 is a diagram showing a schematic configuration of the electric circuit of the IC card door, and FIG. 5 is a diagram showing an example of the configuration of the power supply control circuit. 6 is a timing chart for explaining the operation of the main parts in FIG. 5, FIG. 7 is a schematic block diagram of the calendar circuit, and FIG. 8 is a diagram showing the output timing of the signal from the frequency dividing circuit. , FIG. 9 is a diagram showing an example of the structure of the magnetism generating member control circuit, and FIGS. 10 and 11 are timing charts for explaining the operation of the main parts in FIG. 9. DESCRIPTION OF SYMBOLS 10... IC card (portable medium), 11... Contact part, 12... Keyboard part, 13... Display part, 14... Magnetism generating member, 16... Terminal, 21
... Communication control opening circuit, 23 ... Power supply control circuit, 25.
... Internal battery (power supply), 26... Clock control circuit, 27... Oscillator, 28... CPU <control element), 31... Data memory, 33... Calendar circuit, 34... - Generator (first clock generation circuit), 38
. . . Keyboard interface, 40 . . . Magnetism generating member control circuit, 67 . . . Oscillation circuit (second clock generation circuit). Applicant's agent Patent attorney Takehiko Suzue 2 Figure 45

Claims (4)

[Claims] (1) In a portable medium that has a control element and is operated by an internal power supply, a first clock generation means that constantly generates a low-frequency clock, and a second clock that generates a high-frequency clock generating means; when the control element is activated, the low frequency clock from the first clock generation means is used to operate the control element, and the second clock generation means starts generating a clock; A portable medium comprising: control means for operating a control element using a stable high-frequency clock generated from the second clock generation means after a predetermined period of time has elapsed. (2) The portable medium according to claim 1, wherein the control element is a CPU. (3) The portable medium according to claim 1, wherein the first clock generating means generates a clock for a watch. (4) The portable medium according to claim 1, wherein the control element is activated by key input from a keyboard.