JPS6359266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a thin film transistor using an amorphous semiconductor.

(2) Background of the technology A field-effect thin film transistor is made by depositing a gate electrode, a gate insulating film, an amorphous silicon layer as a semiconductor layer, and source and drain electrodes on a suitable substrate such as a glass plate, for example in a matrix. It is attracting attention as a driving element for large, segmented liquid crystal displays.

FIG. 1 shows an example of this, where 1 is a source electrode and 2 is a gate electrode. These constitute the vertical and horizontal lines of the matrix. Reference numeral 3 denotes a drain electrode, which is rectangular and has a large area, and as shown in the cross-sectional view of Figure b, forms a pair of electrodes of a liquid crystal panel together with a counter electrode 4, and a liquid crystal 5 is sealed between these electrodes. The inter-electrode spacing L is about 10 μm. When source electrode 1 and gate electrode 2 are selected and a voltage is applied, together with those selected source and gate electrodes,
When a source voltage is applied to the drain electrode 3 constituting a TFT (thin film transistor), the alignment of the liquid crystal between the drain electrode and the counter electrode 4 changes, and that part becomes transparent and appears white. In order to express delicate images, a large number of micropixels are required, and the screen needs to be of a certain size, so even if it is an A4 size version, it is necessary to use an IC that uses a chip of several mm square.
Considering the above, it is extremely large, and thin film transistors are suitable for such applications.

(3) Prior Art and Problems Conventionally, there are two methods for manufacturing thin film transistors using amorphous silicon, as shown in FIGS. 2 and 3.

In the method shown in FIG. 2, first, a gate electrode material is deposited on a glass substrate 6 as shown in FIG.
Grow SiO ₂ by the method to form the gate insulating film 8,
Further, an amorphous silicon layer is grown thereon by a plasma CVD method and patterned to form a semiconductor layer 9. Next, as shown in figure b, a positive resist 10 is applied on the semiconductor layer 9, and this is exposed and developed using a photomask 11. Next, as shown in figure c, an electrode material is deposited, and then lifted off to form a source electrode 12. A drain electrode 13 is formed, and finally a passivation film 14 is formed as shown in Figure d.

Next, in the method shown in FIG. 3, a gate electrode material is first deposited on a glass substrate 6 as shown in FIG.
Grow SiO ₂ by CVD method to form gate insulating film 8
shall be. A positive type photoresist 10 is applied thereon as shown in Figure b, exposed using a photomask 11, and developed. Next, as shown in Figure c, an electrode material is deposited and then lifted off to form a source electrode 12 and a drain electrode 13. Next, as shown in figure d, the plasma
An amorphous silicon layer 9 and a passivation film 14 are formed by the CVD method.

In the thin film transistor manufactured by such a manufacturing method, in the first case, there is a drawback that the gate electrode 7 and the source and drain electrodes 12 and 13 overlap greatly, resulting in poor high frequency characteristics. The drawback was that the saturation current was kept low due to the resistance. In addition, in the case of Figure 3, since the channel, source, and drain electrodes 12 and 13 are on the same plane, series resistance is ignored, and although the structure allows for a large saturation current, it is exposed to air after the gate insulating film 8 is formed. Therefore, there was a drawback that there were many interface states in the channel portion due to gas adsorption, contamination, etc., resulting in poor characteristics.

(4) Object of the Invention In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a manufacturing method capable of obtaining a high-performance thin film transistor.

(5) Structure of the Invention According to the present invention, a non-transparent gate electrode is formed on a glass substrate, a transparent gate insulating film is formed on the substrate, and a resist is exposed through the gate electrode itself. A hydrogenated amorphous silicon film and a light-transmitting passivation film of a possible thickness are successively formed without breaking the vacuum, then a positive photoresist is coated on the passivation film, and a glass substrate is coated using the gate electrode as a mask. exposed from the side,
After development, the passivation film is removed by etching using the resist remaining in the same width as the gate electrode as a mask, and ohmic source and drain electrodes are formed on the amorphous silicon film by a lift-off method using the resist pattern. This is achieved by providing a method for manufacturing a self-aligned thin film transistor characterized by the following.

In the above manufacturing method, the passivation film is removed by etching, the amorphous silicon film is further removed by a chemical or physical method, and then the ohmic source and drain electrodes are formed by a lift-off method using the resist pattern. Therefore, a planar electrode arrangement is also possible.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a diagram for explaining a method of manufacturing a self-aligned thin film transistor according to the present invention. In the figure, 15 is a glass substrate, 16 is a non-transparent gate electrode, 17 is a transparent gate insulating film, 18 is an amorphous silicon film, 19 is a transparent passivation film, and 20 is a positive photoresist. , 21 represents a source electrode, and 22 represents a drain electrode, respectively.

An example of the present invention will be explained using FIG. 4.
First, as shown in Figure a, a 0.1 μm thick film of NiCr was formed as a non-transparent gate electrode 16 on a glass substrate 15, and then a 0.3 μm thick film of SiO ₂ was formed as a transparent gate insulating film 17 by plasma CVD. , an amorphous silicon film 18 with a thickness of 50 to 1000 Å is successively formed, and a light-transmitting passivation film 19 is further successively formed.
Deposit a film of 0.5 μm. Next, as shown in figure b, a positive resist 20 of AZ1350J is applied on the passivation film 19.
It is applied to a thickness of 1 μm and irradiated with ultraviolet light 23 for 2 minutes from the glass substrate side. In this state, by developing with AZ1350J developer for 30 seconds, a resist 20' having the same width as the gate electrode 16 remains as shown in Fig. c. In this case, it is also possible to make the resist width 20' smaller than the gate electrode width 16 by lengthening the ultraviolet irradiation time. Next, this resist pattern 2
The passivation film 19 is etched with F108 solution using 0' as a mask. In this case, the F108 solution etches only the SiO ₂ passivation film 19 but not the amorphous silicon film 18, so the etching stops on the amorphous silicon film 18 as shown in Figure d. Next, in this state, aluminum was deposited to a thickness of 0.2 μm using a vapor deposition method.
After the film is formed, the resist 20' is removed with acetone to form a source electrode 21 and a drain electrode 22 as shown in FIG.

The characteristics of the thin film transistor manufactured in the above manner were such that a one-digit increase in current was obtained compared to the conventional thin film transistor.

(7) Effects of the Invention As explained in detail above, the method for manufacturing a self-aligned thin film transistor of the present invention includes a light-transmitting gate insulating film, a thin amorphous silicon film that allows sufficient light to pass through, and a light-transmitting thin film transistor. It is possible to keep each interface clean by growing the passivation film continuously using the plasma CVD method without breaking the vacuum, and the positive resist on the passivation film can be grown from the glass substrate side using the gate electrode as a mask. By making it possible to use a self-alignment method using light exposure, the overlap between the gate electrode and the source and drain electrodes is made extremely small, improving high-frequency characteristics.Furthermore, the use of a planar structure increases saturation current, etc., resulting in high performance. The effect of this method is that it is possible to obtain a thin film transistor with a high quality.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a driving element of a conventional liquid crystal display, FIGS. 2 and 3 are diagrams for explaining a conventional manufacturing method of a thin film transistor,
FIG. 4 is a diagram for explaining a method of manufacturing a self-aligned thin film transistor according to the present invention. In the drawing, 15 is a glass substrate, 16 is a gate electrode, 17 is a gate insulating film, 18 is an amorphous silicon film, 19 is a transparent passivation film, 20 is a positive photoresist, 21 is a source electrode, and 22 is a drain electrode. are shown respectively.

Claims (1)

[Claims] 1. A non-transparent gate electrode is formed on a glass substrate, and then a transparent gate insulating film is formed on the substrate.
A hydrogenated amorphous silicon film with a thickness that allows resist exposure through itself and a transparent passivation film are successively formed without breaking the vacuum, and then a positive photoresist is applied on the passivation film, and the gate electrode After exposing and developing the passivation film from the glass substrate side using the mask as a mask, the passivation film is removed by etching using the resist remaining in the same width as the gate electrode as a mask, and the resist pattern is used to perform a lift-off method to create ohmic properties on the amorphous silicon film. 1. A method for manufacturing a self-aligned thin film transistor, comprising forming a source electrode and a drain electrode.