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JPS6359267B2 - - Google Patents
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JPS6359267B2 - - Google Patents

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Publication number
JPS6359267B2
JPS6359267B2 JP57229255A JP22925582A JPS6359267B2 JP S6359267 B2 JPS6359267 B2 JP S6359267B2 JP 57229255 A JP57229255 A JP 57229255A JP 22925582 A JP22925582 A JP 22925582A JP S6359267 B2 JPS6359267 B2 JP S6359267B2
Authority
JP
Japan
Prior art keywords
type
barrier
layer
semiconductor device
adjustment layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57229255A
Other languages
Japanese (ja)
Other versions
JPS59124169A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP57229255A priority Critical patent/JPS59124169A/en
Publication of JPS59124169A publication Critical patent/JPS59124169A/en
Publication of JPS6359267B2 publication Critical patent/JPS6359267B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/80FETs having rectifying junction gate electrodes

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

発明の技術分野 本発明は、ヘテロ接合構造を有し、2次元電子
ガスを利用して高速動作を可能とした化合物半導
体装置の改良に関する。 従来技術と問題点 従来、この種の化合物半導体装置としては、2
次元電子ガスを供給するn型AlxGa1-xAs電子供
給層上にシヨツトキ金属ゲート電極を直に形成し
た構成になつている。 第1図は前記化合物半導体装置のエネルギ・バ
ンド・モデルであり、1はシヨツトキ金属ゲート
電極、2はn型AlxGa1-xAs電子供給層、3はノ
ン・ドープGaAs半導体基板、4は2次元電子ガ
ス層である。 この化合物半導体装置に於けるゲート電極1に
於ける電子障壁ポテンシヤルはシヨツトキ金属と
n型AlxGa1-xAs結晶との仕事関数の差であるシ
ヨツトキ障壁φBに依つて決定されている。 良く知られているように、ゲート電極1に印加
し得る順方向電圧はシヨツトキ障壁φBを越えな
い範囲に維持する必要があり、前記化合物半導体
装置では高々0.8〔V〕程度である。そして、その
エピタキシヤル成長半導体層の構成上、人為的に
電子障壁をコントロールすることは一般的に不可
能である。従つて、印加ゲート・バイアス電圧の
許容度が小さく、例えば、スイツチング半導体装
置や高周波半導体装置等で閾値電圧を上昇させた
い場合が生じても実現することは困難であつた。 発明の目的 本発明は、前記の如き化合物半導体装置に於け
るゲート電子障壁ポテンシヤルを可変にして、必
要に応じ所望のゲート電子障壁ポテンシヤルを持
つこの種化合物半導体装置を得られるようにする
ものである。 発明の構成 本発明は、ヘテロ接合構造を有する化合物半導
体装置に於けるエピタキシヤル成長半導体層の構
成に於いて、従来のn型AlxGa1-xAs電子供給層
上に更にp型AlyGa1-yAs(1≧y≧0)障壁調節
層を形成したものである。 この障壁調節層はpn接合として利用されるも
のではなく、該障壁調節層に於ける電子をイオン
化するようにして、単に電子障壁をコントロール
する為の役割を果すものである。 このようなエピタキシヤル成長半導体層構成を
採ると、得られる電子障壁はシヨツトキ金属−半
導体結晶界面のシヨツトキ障壁φBではなく、p
型AlyGa1-yAs障壁調節層内に形成されるポテン
シヤル障壁に依り決定される。 第2図はそのような化合物半導体装置のエネル
ギ・バンド・モデルを表わすものであり、図に於
いて、11はシヨツトキ金属ゲート電極、12は
p型AlyGa1-yAs障壁調節層、13はn型Alx
Ga1-xAs電子供給、14はノン・ドープGaAs半
導体基板、15は2次元電子ガス層を表わしてい
る。 ここで得られるポテンシヤル障壁はp型Aly
Ga1-yAs障壁調節層12の厚み、p型不純物のド
ープ量、y値の三つの物理定数に依つて決定さ
れ、最小は従来の構成で得られるシヨツトキ障壁
φB(〜0.8〔eV〕)から、最大はAlAsのバンド・ギ
ヤツプ程度である2.1〔eV〕あたりまでの範囲を
選択的に調節して実現することができる。従つ
て、ゲート電極11に於ける順方向電圧は従来の
場合と比較すると飛躍的に大きくすることが可能
である。 このようなポテンシヤル障壁のみを制御するp
型AlyGa1-yAs障壁調節層12の不純物ドープ量
Na及び膜厚tの関係は、障壁調節層12のy値
が一定で且つy値及びn型AlxGa1-xAs電子供給
層13のx値が同一である場合には次式で与えら
れる。 ここで、EgはAlyGa1-yAsのエネルギ・ギヤツ
プ、NDはn型AlxGa1-xAs電子供給層13のドー
プ量である。 尚、p型AlyGa1-yAs障壁調節層12に於ける
y値を表面で0、即ち、GaAsで終端させるよう
にAlの分布にグレードをつけるようにすれば表
面酸化防止に有効である。 発明の実施例 第3図は本発明一実施例の要部切断側面図であ
る。 図に於いて、21はノン・ドープGaAs半導体
基板、22は2次元電子ガス層、23はn型Alx
Ga1-xAs電子供給層、24はp型AlyGa1-yAs障
壁調節層、25はn+型GaAs電極コンタクト層、
26はアルミニウム・ゲート電極、27は金・ゲ
ルマニウム/金(Au・Ge/Au)オーミツク電
極をそれぞれ示している。 本実施例では、オーミツク電極27の下にはコ
ンタクト抵抗を減少させる為にn+型電極コンタ
クト層25が設けられ、電極金属とGaAs結晶と
のオーミツク合金化層は2次元電子ガス層22に
まで到達している。次に、主たる仕様を列挙する
と次の通りである。 ノン・ドープGaAs半導体基板21 厚さ:約1〔μm〕程度 n型AlxGa1-xAs電子供給層23 厚さ:500〔Å〕程度 不純物濃度:1×1018〔cm-3〕 x値:0.3 p型AlyGa1-yAs障壁調節層24 厚さ:100〜300〔Å〕程度 不純物濃度:2×1018〔cm-3〕 y値:0≧y≧0.3 本実施例に於けるゲート電極26直下の電子障
壁ポテンシヤルは第4図に見られる通りである。 第4図では縦軸に電子障壁ポテンシヤルを単位
〔eV〕で、横軸にp型AlyGa1-yAs障壁調節層2
4の厚みを単位〔Å〕で採つてある。 図から明らかなように、本実施例に於ける電子
障壁ポテンシヤルとしては0.8〜1.2〔eV〕程度の
値が観測される。これは、従来の値よりも遥かに
大きいものである。 発明の効果 本発明は、ヘテロ接合を有し、2次元電子ガス
を利用して高速動作を可能にした化合物半導体装
置に於いて、n型AlxGa1-xAs電子供給層上にp
型AlyGa1-yAs障壁調節層を形成することに依り、
電子障壁ポテンシヤルをシヨツトキ障壁φBから
AlyGa1-yAs障壁調節層のエネルギ・ギヤツプEg
の範囲で任意に変化させることが可能であり、そ
の結果、前記化合物半導体装置のダイナミツク特
性の範囲を拡大することができる。
TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement in a compound semiconductor device having a heterojunction structure and capable of high-speed operation using two-dimensional electron gas. Conventional technology and problems Conventionally, this type of compound semiconductor device has two
The structure is such that a shot metal gate electrode is directly formed on an n-type Al x Ga 1-x As electron supply layer that supplies dimensional electron gas. FIG. 1 shows an energy band model of the compound semiconductor device, in which 1 is a shot metal gate electrode, 2 is an n-type Al x Ga 1-x As electron supply layer, 3 is a non-doped GaAs semiconductor substrate, and 4 is a non-doped GaAs semiconductor substrate. It is a two-dimensional electron gas layer. The electron barrier potential of the gate electrode 1 in this compound semiconductor device is determined by the shot barrier φ B , which is the difference in work function between the shot metal and the n-type Al x Ga 1-x As crystal. As is well known, the forward voltage that can be applied to the gate electrode 1 must be maintained within a range that does not exceed the shot barrier φ B , and in the compound semiconductor device, it is approximately 0.8 [V] at most. Due to the structure of the epitaxially grown semiconductor layer, it is generally impossible to artificially control the electron barrier. Therefore, the tolerance of the applied gate bias voltage is small, and even if it is desired to increase the threshold voltage in, for example, a switching semiconductor device, a high frequency semiconductor device, etc., it is difficult to achieve this. Purpose of the Invention The present invention is to make the gate electron barrier potential in the compound semiconductor device as described above variable, so that it is possible to obtain such a compound semiconductor device having a desired gate electron barrier potential as necessary. . Structure of the Invention The present invention provides a structure of an epitaxially grown semiconductor layer in a compound semiconductor device having a heterojunction structure . A Ga 1-y As (1≧y≧0) barrier adjustment layer is formed. This barrier adjustment layer is not used as a pn junction, but merely serves to control the electron barrier by ionizing electrons in the barrier adjustment layer. When such an epitaxially grown semiconductor layer structure is adopted, the resulting electron barrier is not the shot barrier φ B at the shot metal-semiconductor crystal interface, but the p
It is determined by the potential barrier formed in the type Al y Ga 1-y As barrier adjustment layer. FIG. 2 shows an energy band model of such a compound semiconductor device, and in the figure, 11 is a shot metal gate electrode, 12 is a p-type Al y Ga 1-y As barrier adjustment layer, and 13 is a p-type Al y Ga 1-y As barrier adjustment layer. is n-type Al x
14 represents a non-doped GaAs semiconductor substrate, and 15 represents a two - dimensional electron gas layer. The potential barrier obtained here is p-type Al y
It is determined by three physical constants: the thickness of the Ga 1-y As barrier adjustment layer 12, the amount of p-type impurity doping, and the y value, and the minimum is the shot barrier φ B (~0.8 [eV]) obtained with the conventional configuration. ) to a maximum of around 2.1 [eV], which is about the band gap of AlAs. Therefore, the forward voltage at the gate electrode 11 can be dramatically increased compared to the conventional case. p that controls only such potential barriers
Impurity doping amount of type Al y Ga 1-y As barrier adjustment layer 12
The relationship between Na and film thickness t is given by the following equation when the y value of the barrier adjustment layer 12 is constant and the y value and the x value of the n-type Al x Ga 1-x As electron supply layer 13 are the same. It will be done. Here, Eg is the energy gap of Al y Ga 1-y As, and N D is the doping amount of the n-type Al x Ga 1-x As electron supply layer 13. Note that it is effective to prevent surface oxidation by grading the distribution of Al so that the y value in the p-type Al y Ga 1-y As barrier adjustment layer 12 is 0 at the surface, that is, it is terminated with GaAs. be. Embodiment of the Invention FIG. 3 is a cutaway side view of essential parts of an embodiment of the invention. In the figure, 21 is a non-doped GaAs semiconductor substrate, 22 is a two-dimensional electron gas layer, and 23 is an n-type Al x
Ga 1-x As electron supply layer, 24 p-type Al y Ga 1-y As barrier adjustment layer, 25 n + type GaAs electrode contact layer,
Reference numeral 26 indicates an aluminum gate electrode, and reference numeral 27 indicates a gold/germanium/gold (Au.Ge/Au) ohmic electrode. In this embodiment, an n + type electrode contact layer 25 is provided below the ohmic electrode 27 in order to reduce contact resistance, and the ohmic alloy layer of the electrode metal and GaAs crystal extends to the two-dimensional electron gas layer 22. It has been reached. Next, the main specifications are listed as follows. Non-doped GaAs semiconductor substrate 21 Thickness: approximately 1 [μm] N-type Al x Ga 1-x As electron supply layer 23 Thickness: approximately 500 [Å] Impurity concentration: 1×10 18 [cm -3 ] x Value: 0.3 P-type Al y Ga 1-y As barrier adjustment layer 24 Thickness: About 100 to 300 [Å] Impurity concentration: 2×10 18 [cm -3 ] y value: 0≧y≧0.3 In this example The electron barrier potential directly below the gate electrode 26 is as shown in FIG. In Figure 4, the vertical axis represents the electron barrier potential in units [eV], and the horizontal axis represents the p-type Al y Ga 1-y As barrier adjustment layer 2.
The thickness of 4 is measured in the unit [Å]. As is clear from the figure, the electron barrier potential in this example is observed to be approximately 0.8 to 1.2 [eV]. This is much larger than the conventional value. Effects of the Invention The present invention provides a compound semiconductor device having a heterojunction and capable of high-speed operation using two -dimensional electron gas.
By forming a type Al y Ga 1-y As barrier adjustment layer,
The electron barrier potential is calculated from the shot barrier φ B.
Energy gap Eg of Al y Ga 1-y As barrier adjustment layer
As a result, the range of dynamic characteristics of the compound semiconductor device can be expanded.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のエネルギ・バンド・モデル、
第2図は本発明を適用した場合に於けるエネル
ギ・バンド・モデル、第3図は本発明一実施例の
要部切断側面図、第4図は電子障壁ポテンシヤル
とp型AlyGa1-yAs障壁調節層の厚みとの関係を
表わす線図である。 図に於いて、21はノン・ドープGaAs半導体
基板、22は2次元電子ガス層、23はn型Alx
Ga1-xAs電子供給層、24はp型AlyGa1-yAs障
壁調節層、25はn+型GaAs電極コンタクト層、
26はアルミニウム・ゲート電極、27は金・ゲ
ルマニウム/金オーミツク電極である。
Figure 1 shows the conventional energy band model.
Fig. 2 shows an energy band model when the present invention is applied, Fig. 3 is a cutaway side view of essential parts of an embodiment of the present invention, and Fig. 4 shows electron barrier potential and p-type Al y Ga 1- y is a diagram showing the relationship with the thickness of the As barrier adjustment layer. In the figure, 21 is a non-doped GaAs semiconductor substrate, 22 is a two-dimensional electron gas layer, and 23 is an n-type Al x
Ga 1-x As electron supply layer, 24 p-type Al y Ga 1-y As barrier adjustment layer, 25 n + type GaAs electrode contact layer,
26 is an aluminum gate electrode, and 27 is a gold/germanium/gold ohmic electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 AlGaAs/GaAsのヘテロ接合構造を有し2
次元電子ガスを利用して高速動作をおこなう化合
物半導体装置に於いて、n型AlGaAs電子供給層
上にp型AlyGa1-yAs(1≧y≧0)障壁調節層が
設けられ、p型AlyGa1-yAs(1≧y≧0)障壁調
節層の表面にシヨツトキ・ゲート電極が設けられ
てなり、更に当該表面はy=0でGaAsにて終端
されるようAlが分布されていることを特徴とす
る化合物半導体装置。
1 Has a heterojunction structure of AlGaAs/GaAs 2
In a compound semiconductor device that performs high-speed operation using dimensional electron gas, a p-type Al y Ga 1-y As (1≧y≧0) barrier adjustment layer is provided on the n-type AlGaAs electron supply layer, A shot gate electrode is provided on the surface of the type Al y Ga 1-y As (1≧y≧0) barrier adjustment layer, and furthermore, Al is distributed on the surface so that it is terminated with GaAs at y=0. A compound semiconductor device characterized by:
JP57229255A 1982-12-29 1982-12-29 Compound semiconductor device Granted JPS59124169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57229255A JPS59124169A (en) 1982-12-29 1982-12-29 Compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57229255A JPS59124169A (en) 1982-12-29 1982-12-29 Compound semiconductor device

Publications (2)

Publication Number Publication Date
JPS59124169A JPS59124169A (en) 1984-07-18
JPS6359267B2 true JPS6359267B2 (en) 1988-11-18

Family

ID=16889239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57229255A Granted JPS59124169A (en) 1982-12-29 1982-12-29 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS59124169A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59149063A (en) * 1983-02-16 1984-08-25 Nec Corp semiconductor equipment

Also Published As

Publication number Publication date
JPS59124169A (en) 1984-07-18

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